user can help keep AVDD
參數(shù)資料
型號： ADUC831BSZ
廠商： Analog Devices Inc
文件頁數(shù)： 59/76頁
文件大小： 0K
描述： IC ADC/DAC 12BIT W/MCU 52-MQFP
產(chǎn)品培訓模塊： Process Control
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
產(chǎn)品目錄頁面： 738 (CN2011-ZH PDF)
配用： EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
–62–
ADuC831
As an alternative to providing two separate power supplies, the
user can help keep AVDD quiet by placing a small series resistor
and/or ferrite bead between it and DVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 61. With this configuration other analog circuitry
(such as op amps, voltage reference, and so on) can be powered
from the AVDD supply line as well. The user will still want to
include back-to-back Schottky diodes between AVDD and DVDD
in order to protect from power-up and power-down transient con-
ditions that could separate the two supply voltages momentarily.
DVDD
ADuC831
AGND
AVDD
0.1 F
10 F
DGND
0.1 F
DIGITAL SUPPLY
–
+
BEAD
1.6V
Figure 61. External Single-Supply Connections
Notice that in both Figure 60 and Figure 61, a large value (10
F)
reservoir capacitor sits on DVDD and a separate 10
F capacitor
sits on AVDD. Also, local small-value (0.1
F) capacitors are located at
each VDD pin of the chip. As per standard design practice, be sure
to include all of these capacitors, and ensure the smaller capacitors
are close to each AVDD pin with trace lengths as short as possible.
Connect the ground terminal of each of these capacitors directly to
the underlying ground plane. Finally, it should also be noted that,
at all times, the analog and digital ground pins on the ADuC831
must be referenced to the same system ground reference point.
Power Consumption
The currents consumed by the various sections of the ADuC831
are shown in Table XXXIII. The CORE values given represent
the current drawn by DVDD, while the rest (ADC, DAC, voltage
ref) are pulled by the AVDD pin and can be disabled in software
when not in use. The other on-chip peripherals (watchdog timer,
power supply monitor, and so on) consume negligible current
and are therefore lumped in with the Core operating current here.
Of course, the user must add any currents sourced by the parallel
and serial I/O pins, and that sourced by the DAC, in order to
determine the total current needed at the ADuC831’s supply pins.
Also, current drawn from the DVDD supply will increase by
approximately 10 mA during Flash/EE erase and program cycles.
Table XXXIII. Typical IDD of Core and Peripherals
VDD = 5 V
VDD = 3 V
Core:
(Normal Mode) (1.6 nAs
MCLK) +
(0.8 nAs
MCLK) +
6 mA
3 mA
Core:
(Idle Mode)
(0.75 nAs
MCLK) +
(0.25 nAs
MCLK)+
5 mA
3 mA
ADC:
1.3 mA
1.0 mA
DAC (Each):
250
A
200
A
Voltage Ref:
200
A
150
A
Since operating DVDD current is primarily a function of clock
speed, the expressions for CORE supply current in Table XXXIII
are given as functions of MCLK, the oscillator frequency. Plug in
a value for MCLK in hertz to determine the current consumed by
the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. And again, do not forget
to include current sourced by I/O pins, serial port pins, DAC
outputs, and so forth, plus the additional current drawn during
Flash/EE erase and program cycles.
A software switch allows the chip to be switched from normal
mode into idle mode, and also into full power-down mode.
Below are brief descriptions of power-down and idle modes.
Power Saving Modes
In idle mode, the oscillator continues to run but is gated off to the
core only. The on-chip peripherals continue to receive the clock,
and remain functional. Port pins and DAC output pins retain their
states in this mode. The chip will recover from idle mode upon
receiving any enabled interrupt, or on receiving a hardware reset.
In full power-down mode, the on-chip oscillator stops and all
on-chip peripherals are shut down. Port pins retain their logic
levels in this mode, but the DAC output goes to a high-impedance
state (three-state). During full power-down mode, the ADuC831
consumes a total of approximately 15
A. There are five ways of
terminating power-down mode:
Asserting the RESET Pin (Pin 15)
Returns to normal mode. All registers are set to their default
state and program execution starts at the reset vector once the
Reset pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR will return the
core to the instruction after that which enabled power-down.
I
2C or SPI Interrupt
Power-down mode is terminated and the CPU services the I
2C/SPI
interrupt. The RETI at the end of the ISR will return the core to
the instruction after that which enabled power-down. It should be
noted that the I
2C/SPI power down interrupt enable bit (SERIPD)
in the PCON SFR must first be set to allow this mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the
INT0
interrupt. The RETI at the end of the ISR will return the core
to the instruction after that which enabled power-down. It should
be noted that the
INT0 power-down interrupt enable bit (INT0PD)
in the PCON SFR must first be set to allow this mode of operation.
Power-On Reset
An internal POR (Power-On Reset) is implemented on the
ADuC831. For DVDD below 2.45 V, the internal POR will hold
the ADuC831 in reset. As DVDD rises above 2.45 V an internal
timer will timeout for approximately 128 ms before the part is
released from reset with a 16 MHz crystal. With other crystal
values the timeout will increase. The user must ensure that the
power supply has reached a stable 2.7 V minimum level by this
time. Likewise on power-down, the internal POR will hold the
ADuC831 in reset until the power supply has dropped below 1 V.
Figure 62 illustrates the operation of the internal POR in detail.
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