參數(shù)資料
型號(hào)： ADUC831BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/76頁(yè)
文件大?。?/td> 0K
描述： IC ADC/DAC 12BIT W/MCU 52-MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
配用： EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
–56–
ADuC831
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RxD.
TxD outputs the shift clock. Eight data bits are transmitted or
received. Transmission is initiated by any instruction that writes
to SBUF. The data is shifted out of the RxD line. The eight bits
are transmitted with the least-significant bit (LSB) first, as shown
in Figure 51.
CORE
CLK
ALE
RxD
(DATA OUT)
TxD
(SHIFT CLOCK)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
S6
S5
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
MACHINE
CYCLE 8
MACHINE
CYCLE 7
MACHINE
CYCLE 2
MACHINE
CYCLE 1
Figure 51. UART Serial Port Transmission, Mode 0
Reception is initiated when the receive enable bit (REN) is 1 and
the receive interrupt bit (RI) is 0. When RI is cleared the data is
clocked into the RxD line and the clock pulses are output from
the TxD line.
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, 10 bits are transmitted on TxD or
received on RxD. The baud rate is set by the Timer 1 or Timer 2
overflow rate, or a combination of the two (one for transmission
and the other for reception).
Transmission is initiated by writing to SBUF. The “write to
SBUF” signal also loads a 1 (stop bit) into the ninth bit position
of the transmit shift register. The data is output bit by bit until
the stop bit appears on TxD and the transmit interrupt flag (TI)
is automatically set as shown in Figure 52.
TxD
TI
(SCON.1)
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
SET INTERRUPT
i.e., READY FOR MORE DATA
Figure 52. UART Serial Port Transmission, Mode 0
Reception is initiated when a 1-to-0 transition is detected on RxD.
Assuming a valid start bit was detected, character reception
continues. The start bit is skipped and the eight data bits are
clocked into the serial port shift register. When all eight bits
have been clocked in, the following events occur:
The eight bits in the receive shift register are latched into SBUF.
The ninth bit (Stop bit) is clocked into RB8 in SCON.
The Receiver Interrupt flag (RI) is set.
This will be the case if, and only if, the following conditions are
met at the time the final shift pulse is generated:
RI = 0, and either SM2 = 0, or SM2 = 1 and the received
stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 2: 9-Bit UART with Fixed Baud Rate
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_Clk/32. Eleven bits are transmitted or received, a start
bit (0), eight data bits, a programmable ninth bit, and a stop bit
(1). The ninth bit is most often used as a parity bit, although it
can be used for anything, including a ninth data bit if required.
To transmit, the eight data bits must be written into SBUF.
The ninth bit must be written to TB8 in SCON. When trans-
mission is initiated, the eight data bits (from SBUF) are loaded
onto the transmit shift register (LSB first). The contents of TB8
are loaded into the ninth bit position of the transmit shift regis-
ter. The transmission will start at the next valid baud rate clock.
The TI flag is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RxD (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
The eight bits in the receive shift register are latched into SBUF.
The ninth data bit is latched into RB8 in SCON.
The Receiver Interrupt flag (RI) is set.
This will be the case if, and only if, the following conditions are
met at the time the final shift pulse is generated:
RI = 0, and either SM2 = 0, or SM2 = 1 and the received stop
bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3: 9-Bit UART with Variable Baud Rate
Mode 3 is selected by setting both SM0 and SM1. In this mode,
the 8051 UART serial port operates in 9-bit mode with a vari-
able baud rate determined by either Timer 1 or Timer 2. The
operation of the 9-bit UART is the same as for Mode 2 but the
baud rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated
in Mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
Mode
Baud Rate = (Core Clock Frequency /
)
012
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode
Baud Rate = (
/
)
Core Clock Frequency)
SMOD
22
64
× (
Mode 1 and 3 Baud Rate Generation
The baud rates in Modes 1 and 3 are determined by the overflow
rate in Timer 1 or Timer 2, or both (one for transmit and the
other for receive).
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