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參數(shù)資料
| 型號： | ADUC832BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52MQFP |
| 產(chǎn)品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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Data Sheet
ADuC832
Rev. B | Page 57 of 92
MODE 4: DUAL NRZ 16-BIT Σ-Δ DAC
Mode 4 provides a high speed PWM output similar to that of a
Σ-Δ DAC. Typically, this mode is used with the PWM clock
equal to 16.777216 MHz.
In this mode, P2.6 and P2.7 are updated every PWM clock
(60 ns in the case of 16 MHz). Over every 65,536 cycles (16-bit
PWM) PWM0 (P2.6) is high for PWM0H/PWM0L cycles and
low for (65,536 PWM0H/L) cycles. Similarly PWM1 (P2.7) is
high for PWM1H/PWM1L cycles and low for (65,536
PWM1H/PWM1L) cycles.
For example, if PWM1H/L was set to 4010H (slightly above one
quarter of FS), then typically P2.7 is low for three clocks and
high for one clock (each clock is approximately 60 ns). Over
every 65,536 clocks, the PWM compensates for the fact that the
output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
16.78MHz
16-BIT
60s
0
16-BIT
CARRY OUT AT P1.0
CARRY OUT AT P2.7
PWM0H/L = C000H
PWM1H/L = 4000H
0
1
0
LATCH
0
1
0
02987-
049
Figure 60. PWM Mode 4
For faster DAC outputs (at lower resolution) write 0s to the
LSBs that are not required. If, for example, only 12-bit perfor-
mance is required, then write 0s to the four LSBs. This means
that a 12-bit accurate Σ-Δ DAC output can occur at 4.096 kHz.
Similarly, writing 0s to the eight LSBs gives an 8-bit accurate
Σ-Δ DAC output at 65 kHz.
MODE 5: DUAL 8-BIT PWM
In Mode 5, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are individually programmable. The
maximum resolution of the PWM output is eight bits. The
output resolution is set by the PWM1L and PWM1H SFRs for
the P2.6 and P2.7 outputs, respectively. PWM0L and PWM0H
set the duty cycles of the PWM outputs at P2.6 and P2.7,
respectively. Both PWMs have same clock source and clock
divider.
P2.7
P2.6
PWM COUNTERS
PWM1H
0
PWM1L
PWM0H
PWM0L
02987-
050
Figure 61. PWM Mode 5
MODE 6: DUAL RZ 16-BIT Σ-Δ DAC
Mode 6 provides a high speed PWM output similar to that of a
Σ-Δ DAC. Mode 6 operates very similarly to Mode 4. However,
the key difference is that Mode 6 provides return-to-zero (RZ)
Σ-Δ DAC output. Mode 4 provides nonreturn-to-zero Σ-Δ DAC
outputs. The RZ mode ensures that any difference in the rise
and fall times does not affect the Σ-Δ DAC INL. However, the
RZ mode halves the dynamic range of the Σ-Δ DAC outputs
from 0 V AVDD down to 0 V AVDD/2. For best results, this
mode should be used with a PWM clock divider of four.
If PWM1H is set to 4010H (slightly above one quarter of FS)
then typically P2.7 is low for three full clocks (3 × 60 ns), high
for half a clock (30 ns), and then low again for half a clock
(30 ns) before repeating itself. Over every 65,536 clocks, the
PWM compensates for the fact that the output should be slightly
above one quarter of full scale by occasionally leaving the
output high for two half clocks in four.
4MHz
16-BIT
240 s
0
16-BIT
CARRY OUT AT P2.6
CARRY OUT AT P2.7
PWM0H/L = C000H
PWM1H/L = 4000H
0
1
0
LATCH
0
1
0
240 s
0, 3/4, 1/2, 1/4, 0
02987-
051
Figure 62. PWM Mode 6
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