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參數(shù)資料
| 型號： | ADUC832BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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Data Sheet
ADuC832
Rev. B | Page 67 of 92
8052-COMPATIBLE ON-CHIP PERIPHERALS
This section gives a brief overview of the various secondary
peripheral circuits that are also available to the user on chip.
These remaining functions are mostly 8052 compatible (with a
few additional features) and are controlled via standard 8052 SFR
bit definitions.
PARALLEL I/O
The ADuC832 uses four input/output ports to exchange data
with external devices. In addition to performing general-purpose
I/O, some ports are capable of external memory operations
whereas others are multiplexed with alternate functions for the
peripheral features on the device. In general, when a peripheral
is enabled, that pin cannot be used as a general-purpose I/O pin.
PORT 0
Port 0 is an 8-bit, open-drain, bidirectional I/O port that is directly
controlled via the Port 0 SFR. Port 0 is also the multiplexed low
order address and data bus during accesses to external program
or data memory.
Figure 66 shows a typical bit latch and I/O buffer for a Port 0
port pin. The bit latch (one bit in the port’s SFR) is represented
as a Type D flip-flop, which clocks in a value from the internal
bus in response to a write-to-latch signal from the CPU. The Q
output of the flip-flop is placed on the internal bus in response
to a read latch signal from the CPU. The level of the port pin
itself is placed on the internal bus in response to a read pin
signal from the CPU. Some instructions that read a port activate
the read latch signal, and others activate the read pin signal. See
the Read-Modify-Write Instructions section for more details.
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
ADDR/DATA
P0.x
PIN
02987-
055
Q
Figure 66. Port 0 Bit Latch and I/O Buffer
As shown in Figure 66, the output drivers of Port 0 pins are
switchable to an internal ADDR and ADDR/data bus by an
internal control signal for use in external memory accesses.
During external memory accesses, 1s are written to the P0 SFR
(that is, all of its bit latches become 1). When accessing external
memory, the control signal in Figure 66 goes high, enabling
push-pull operation of the output pin from the internal address
or data bus (ADDR/data line). Therefore, no external pull-ups
are required on Port 0 for it to access external memory.
In general-purpose I/O port mode, Port 0 pins that have 1s
written to them via the Port 0 SFR are configured as open drain
and therefore float. In this state, Port 0 pins can be used as high
impedance inputs. This is represented in Figure 66 by the
NAND gate whose output remains high as long as the control
signal is low, thereby disabling the top FET. External pull-up
resistors are therefore required when Port 0 pins are used as
general-purpose outputs. Port 0 pins with 0s written to them drive
a logic low output voltage (VOL) and are capable of sinking 1.6 mA.
PORT 1
Port 1 is also an 8-bit port directly controlled via the P1 SFR.
Port 1 digital output capability is not supported on this device.
Port 1 pins can be configured as digital inputs or analog inputs.
By (power-on) default, these pins are configured as analog
inputs, that is, 1 written in the corresponding Port 1 register bit.
To configure any of these pins as digital inputs, write a 0 to
these port bits to configure the corresponding pin as a high
impedance digital input.
These pins also have various secondary functions described in
Table 34. Port 1, Alternate Pin Functions
Pin
Alternate Function
P1.0
T2 (Timer/Counter 2 external input) or ADC0 (single-
ended analog input)
P1.1
T2EX (Timer/Counter 2 capture/reload trigger) or ADC1
P1.5
SS (slave select for the SPI interface) or ADC5
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
P1.x
PIN
TO ADC
02987-
056
Q
Figure 67. Port 1 Bit Latch and I/O Buffer
PORT 2
Port 2 is a bidirectional port with internal pull-up resistors
directly controlled via the P2 SFR. Port 2 also emits the high
order address bytes during fetches from external program
memory and middle and high order address bytes during
accesses to the 24-bit external data memory space.
As shown in Figure 68, the output drivers of Port 2 are
switchable to an internal ADDR and ADDR/data bus by an
internal control signal for use in external memory accesses (as
for Port 0). In external memory addressing mode (control = 1), the
port pins feature push-pull operation controlled by the internal
address bus (ADDR line). However, unlike the P0 SFR during
external memory accesses, the P2 SFR remains unchanged.
In general-purpose I/O port mode, Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups
(see Figure 69) and, in that state, can be used as inputs. As
inputs, Port 2 pins pulled externally low source current because
of the internal pull-up resistors. Port 2 pins with 0s written to
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| ADUC832BSZ-REEL | 功能描述:IC MCU 62K FLASH ADC/DAC 52MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC832QS-U1 | 制造商:Analog Devices 功能描述:EVAL KIT - Bulk |
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