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參數(shù)資料
| 型號： | ADUC832BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52MQFP |
| 產品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADuC832
Data Sheet
Rev. B | Page 60 of 92
I2C-COMPATIBLE INTERFACE
The ADuC832 supports a fully licensed I2C serial interface. The
I2C interface is implemented as a full hardware slave and soft-
ware master. SDATA is the data I/O pin and SCLOCK is the
serial clock. These two pins are shared with the MOSI and
SCLOCK pins of the on-chip SPI interface. Therefore, the user
can only enable one interface or the other at any given time
(see SPE in SPICON in Table 28). The uC001 Technical Note,
MicroConverter I2C Compatible Interface, describes the opera-
tion of this interface as implemented, and is available from the
MicroConverter website at www.analog.com/microconverter.
I2C INTERFACE SFRs
Three SFRs are used to control the I2C interface. These are
described in the following sections.
I2CCON (I2Control Register)
SFR Address:
E8H
Power-On Default Value:
00H
Bit Addressable:
Yes
I2CADD (I2C Address Register)
SFR Address:
9BH
Power-On Default Value:
55H
Bit Addressable:
No
The I2CADD SFR holds the I2C peripheral address for the part.
It can be overwritten by user code. Technical Note uC001 at
www.analog.com/microconverter describes the format of the
I2C standard 7-bit address in detail.
I2CDAT (I2C Data Register)
SFR Address:
9AH
Power-On Default Value:
00H
Bit Addressable:
No
The I2CDAT SFR is written by the user to transmit data over
the I2C interface or read by user code to read data just received
by the I2C interface. Accessing I2CDAT automatically clears any
pending I2C interrupt and the I2CI bit in the I2CCON SFR. User
software should only access I2CDAT once per interrupt cycle.
Table 29. I2CCON SFR Bit Designations
Bit
Name
Description
[7]
MDO
I2C software master data output bit (master mode only). This data bit is used to implement a master I2C transmitter interface
in software. Data written to this bit is output on the SDATA pin if the data output enable (MDE) bit is set.
[6]
MDE
I2C software master data output enable bit (master mode only). Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
[5]
MCO
I2C software master clock output bit (master mode only). This data bit is used to implement a master I2C transmitter interface
in software. Data written to this bit is output on the SCLOCK pin.
[4]
MDI
I2C software master data input bit (master mode only). This data bit is used to implement a master I2C receiver interface in
software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.
[3]
I2CM
I2C master/slave mode bit set by user to enable I2C software master mode. Cleared by user to enable I2C hardware slave
mode.
[2]
I2CRS
I2C reset bit (slave mode only). Set by user to reset the I2C interface. Cleared by user code for normal I2C operation.
[1]
I2CTX
I2C direction transfer bit (slave mode only). Set by the MicroConverter if the interface is transmitting. Cleared by the
MicroConverter if the interface is receiving.
[0]
I2CI
I2C interrupt bit (slave mode only). Set by the MicroConverter after a byte has been transmitted or received. Cleared
automatically when user code reads the I2CDAT SFR (see the I2CADD (I2C Address Register) section).
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