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參數(shù)資料
| 型號： | ADV7152 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器) |
| 中文描述： | 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 3/32頁 |
| 文件大小： | 322K |
| 代理商： | ADV7152 |
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ADV7152
–11–
REV. B
Color data is latched into the parts pixel port on every rising
edge of LOADIN (see Timing Waveform, Figure 3). The
required frequency of LOADIN is determined by the multiplex
rate, where
fLOADIN = fCLOCK/2
2:1 Multiplex Mode
fLOADIN = fCLOCK
1:1 Multiplex Mode
Other pixel data signals latched into the device by LOADIN
include
SYNC, BLANK and PS0–PS1.
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and
CLOCK. The LOADIN con-
trol signal needs only have a frequency synchronous relationship
to the pixel CLOCK (see “Pipeline Delay & Onboard Calibra-
tion” section). A completely phase-independent LOADIN signal
can be used with the ADV7152, allowing the CLOCK to occur
anywhere during the LOADIN cycle.
Alternatively, the LOADOUT signal of the ADV7152 can be
used. LOADOUT can be connected either directly or indirectly
to LOADIN. Its frequency is automatically set to the correct
LOADIN requirement.
SYNC, BLANK
The
BLANK and SYNC video control signals drive the analog
outputs to the blanking and
SYNC levels respectively. These
signals are latched into the part on the rising edge of LOADIN.
The
SYNC information is encoded onto the IOG analog signal
when bit CR22 of Command Register 2 is set to a Logic “1.”
The
SYNC input is ignored if CR22 is set to “0.”
SYNCOUT
In some applications where it is not permissible to encode
SYNC on green (IOG), SYNCOUT can be used as a separate
TTL digital
SYNC output. This has the advantage over an inde-
pendent (of the ADV7150)
SYNC in that it does not necessitate
knowing the absolute pipeline delay of the part. This allows
complete independence between LOADIN/Pixel Data and
CLOCK. The
SYNC input is connected to the device as normal
with Bit CR22 of Command Register 2 set to “0” thereby pre-
venting
SYNC from being encoded onto IOG. Bit CR12 of
Command Register 1 is set to “1,” enabling
SYNCOUT. The
output signal generates a TTL
SYNCOUT with correct pipeline
delay that is capable of directly driving the composite
SYNC
signal of a computer monitor.
PS0–PS1 (Palette Priority Select Inputs)
These pixel port select inputs determine whether or not the de-
vice is selected. These controls effectively determine whether the
devices RGB analog outputs are turned on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. This state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. These controls allow for switching
between multiple palette devices (see Appendix 4). If the values
of PS0 and PS1 match the values programmed into bits MR16
and MR17 of the Mode Register, then the device is selected; if
there is no match the device is effectively shut down.
Multiplexing
The onboard multiplexers of the ADV7152 eliminate the need
for external data serializer circuits. Multiple video memory de-
vices can be connected, in parallel, directly to the device. Fig-
ure 11 shows two memory banks of 50 MHz memory connected
to the ADV7152, running in 2:1 multiplex mode, giving a
resultant pixel or dot clock rate of 100 MHz. As mentioned in
the previous section, the ADV7152 supports a number of color
data formats in 2:1 and 1:1 multiplex modes.
In 1:1 multiplex mode, the ADV7152 is clocked using the
LOADIN signal. This means that there is no requirement for
differential ECL inputs on CLOCK and
CLOCK. The pixel
clock is connected directly to LOADIN. (Note: The ECL
CLOCK can still be used to generate LOADOUT PRGCKOUT,
etc.)
VRAM (BANK A)
VRAM (BANK B)
MULTIPLEXER
24
ADV7152
VIDEO MEMORY/
FRAME BUFFER
100MHz
(2 x 50MHz)
50MHz
A
B
Figure 11. Direct Interfacing of Video Memory to
ADV7152
CLOCK CONTROL CIRCUIT
The ADV7152 has an integrated Clock Control Circuit (Figure
12). This circuit is capable of generating both the ADV7152’s
internal clocking signals and external graphics subsystem clock-
ing signals. Total system synchronization can be attained by us-
ing the parts output clocking signals to drive the controlling
graphics processor’s master clock as well as the video frame
buffers shift clock signals.
CLOCK,
CLOCK Inputs
The Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and
CLOCK. These inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
CLOCK
ADV7152
CLOCK
DIVIDE BY N
(
÷ N)
LOADOUT
DIVIDE BY M
(
÷ M)
PRGCKOUT
LOADIN
SCKOUT
SCKIN
BLANK
LATCH
ENABLE
SYNC
TO COLOR DATA
MULTIPLEXER
ECL
TO
TTL
M IS A FUNCTION OF MULTIPLEX RATE
M = 2 IN 2:1 MULTIPLEX MODE
M = 1 IN 1:1 MULTIPLEX MODE
N IS INDEPENDENTLY
PROGRAMMABLE
N= (4, 8, 16, 32)
Figure 12. Clock Control Circuit of the ADV7152
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| adv7152es | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADV7152KS110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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