
ADV7152
–16–
REV. B
Data is read from the color palette by first writing to the address
register of the color palette location to be read. The MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. This pointer is reset to red after a blue read or whenever
the address register is written. The address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
The address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
Register Accesses
The MPU can write to or read from all of the ADV7152s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. The Control Registers are accessed indirectly. The
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface Truth Tables
illustrate the structure and protocol for device communication
over the MPU port.
Table III. Interface Truth Table (10-Bit Databus Mode)
R/
W
C1
C0
Databus (D9–D0)
Operation
Result
0
1
DB7–DB0
Write to Mode Register
DB7–DB0 MR17–MR10
0
DB7–DB0
Write to Address Register
DB7–DB0 A7–A0
0
1
0
DB7–DB0
Write to Control Registers
DB7–DB0 Control Register
(Particular Control Register Determined by Address Register)
0
1
DB9–DB0
Write to RED Register
DB9–DB0 R9–R0
0
1
DB9–DB0
Write to GREEN Register
DB9–DB0 G9–G0
0
1
DB9–DB0
Write to BLUE Register
DB9–DB0 B9–B0
Write RGB Data to RAM Location Pointed to by Address Register (A7–A0)
Address Register = Address Register + 1
1
DB7–DB0
Read Mode Register
MR17–MR10 DB7–DB0
1
0
DB7–DB0
Read Address Register
A7–A0 DB7–DB0
1
0
DB7–DB0
Read Control Registers
Register Data DB7–DB0
(Particular Control Register Determined by Address Register)
1
0
1
DB9–DB0
Read RED RAM Location
R9–R0 DB9–DB0
1
0
1
DB9–DB0
Read GREEN RAM Location
G9–G0 DB9–DB0
1
0
1
DB9–DB0
Read BLUE RAM Location
B9–B0 DB9–DB0
(RAM Location Pointed to by Address Reg (A7–A0))
Address Register = Address Register + 1
DB = Data Bit.
ADDRESS REG =
ADDRESS REG + 1
MODE REGISTER
(MR17–MR10)
ADDRESS REGISTER
(A7–A0)
CONTROL
REGISTERS
PIXEL TEST REGISTER
COMMAND REGISTER 2
* THIS REGISTER IS READ ONLY.
LOOK-UP TABLE RAM
(256 x 30)
RED
REGISTER
(R9–R0)
POINTS TO LOCATION
CORRESPONDING TO
ADDRESS REG (A7–A0)
C1 = 0
C0 = 1
C1 = 1
C0 = 1
C1 = 0
C0 = 0
DAC TEST REGISTER
R
G
B
C1 = 1
C0 = 0
R
G
B
ID REGISTER (READ ONLY)
PIXEL MASK REGISTER
COMMAND REGISTER 3
RESERVED
* (READ ONLY)
RESERVED
* (READ ONLY)
RESERVED
* (READ ONLY)
REVISION REGISTER
SYNC, BLANK & IPLL
TEST REGISTER
ADDRESS
REGISTER
(A7–A0)
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
00H
01H
02H
GREEN
REGISTER
(G9–G0)
BLUE
REGISTER
(B9–B0)
COMMAND REGISTER 1
Figure 26. Internal Register Configuration and Address Decoding