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參數(shù)資料
| 型號(hào)： | ADV7152 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器) |
| 中文描述： | 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 322K |
| 代理商： | ADV7152 |
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ADV7152
–15–
REV. B
Table II. Databus Width Table
Databus
RAM/DAC
Read/Write
Width
Resolution
Mode
10 Bit
10-Bit Parallel
10 Bit
8 Bit
8-Bit Parallel
8 Bit
10 Bit
8+2 Byte
8 Bit
8-Bit Parallel
Register Mapping
The ADV7152 contains a number of onboard registers includ-
ing the Mode Register (MR17–MR10), Address Register (A7–
A0) and nine Control Registers as well as Red (R9–R0), Green
(G9–G0) and Blue (B9–B0) Color Registers. These registers
control the entire operation of the part. Figure 26 shows the
internal register configuration.
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and look-up table RAM or
the control registers. If C1, C0 = 1, 0, the MPU has access to
whatever control register is pointed to by the Address Register
(A7–A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up
Table RAM (Color Palette) through the associated color regis-
ters. The
CE input latches data to or from the part.
The R/
W control input determines between read or write ac-
cesses. The Truth Tables III and IV show all modes of access to
the various registers and color palette for both the 8-bit wide
databus configuration and 10-bit wide databus configuration. It
should be noted that after power-up, the devices MPU port is
automatically set to 10-bit wide operation (see Power-On Reset
section).
Color Palette Accesses
Data is written to the color palette by first writing to the address
register of the color palette location to be modified. The MPU
performs three successive write cycles for each of the red, green
and blue registers (10-bit or 8-bit). An internal pointer moves
from red to green to blue after each write is completed. This
pointer is reset to red after a blue write or whenever the address
register is written. During the blue write cycle, the three bytes of
red, green and blue are concatenated into a single 30-bit/24-bit
word and written to the RAM location as specified in the ad-
dress register (A7–A0). The address register then automatically
increments to point to the next RAM location and a similar red,
green and blue palette write sequence is performed. The address
register resets to 00H following a blue write cycle to color pal-
ette RAM location FFH.
PIXEL
INPUT
DATA
PIN
ASSIGN-
MENTS
DATA
LATCHED
TO
PIXEL
PORT
DATA
INTERNALLY
SHIFTED
TO 5 LSBS
B7
B6
B5
B4
B3
B2
B1
B0
x
R7
R6
R5
R4
R3
R2
R1
R0
R4
R3
R2
R1
R0
G4
G3
G2
G4
G3
G2
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
x
G1
G0
B4
B3
B2
B1
B0
B2
B1
B0
x
G1
G0
B4
B3
DATA LATCHES
FIRST 32
LOCATIONS
OF RAM
5
10
TO
BLUE
DAC
0
B4
B3
B2
B1
B0
LOCATION "0"
LOCATION "31"
256 x 10 RAM
(BLUE LUT)
TO
RED
DAC
10
0
R4
R3
R2
R1
R0
256 x 10 RAM
(RED LUT)
LOCATION "0"
LOCATION "31"
TO
GREEN
DAC
10
G4
G3
G2
G1
G0
0
256 x 10 RAM
(GREEN LUT)
LOCATION "0"
LOCATION "31"
5
x
Figure 24. 15-Bit True-Color Mapping Using R0–R7
and G0–G6
MICROPROCESSOR (MPU) PORT
The ADV7152 supports a standard MPU Interface. All the
functions of the part are controlled via this MPU port. Direct
access is gained to the Address Register, Mode Register and all
the Control Registers as well as the Color Palette. The follow-
ing sections describe the setup for reading and writing to all of
the device’s registers.
MPU Interface
The MPU interface (Figure 25) consists of a bidirectional,
10-bit wide databus and interface control signals
CE, C0, C1
and R/
W. The 10-bit wide databus is user configurable as
illustrated.
30
MPU PORT
D0 – D9
10 (8+2)
C0
C1
COMMAND
REGISTERS
(CR1–CR3)
(MR1)
DATA TO
PALETTES
CONTROL REGISTERS
COLOR REGISTERS
ADDRESS
REGISTER
MODE
REGISTER
ID
REGISTER
BLUE
REGISTER
CE
R/W
GREEN
REGISTER
RED
REGISTER
PIXEL MASK
REGISTER
TEST
REGISTERS
REVISION
REGISTER
ADDR
(A7–A0)
Figure 25. MPU Port and Register Configuration
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