參數(shù)資料
型號： ADV7180BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 108/116頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 64-LQFP
產(chǎn)品變化通告： ADV7180 Metal Mask Edit 22/Oct/2009
設(shè)計資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADV7180BSTZ-REELDKR
Data Sheet
ADV7180
Rev. I | Page 91 of 116
Main Map
Bit Description
Bits
(Shading Indicates Default State)
Comments
Notes
Subaddress
Register
7
6
5
4
3
2
1
0
0x2E
Chroma Gain
Control 2,
Chroma Gain2
(CG)
CMG[7:0]/CG[7:0]; chroma
manual gain lower eight
bits; see CMG[11:8]/
CG[11:8] for description
0
CMG[11:0] = see the CMG section
Min value = 0d,
Max value = 4095d
0x2F
Luma Gain
Control 1, Luma
Gain1 (LG)
LMG[11:8]/LG[11:8]; in
manual mode, luma gain
control can be used to
program a desired manual
luma gain; in auto mode,
it can be used to read back
the actual gain value used
x
LAGC[1:0] settings decide in which
mode LMG[11:0] operates
Reserved
1
Set to 1
LAGT[1:0]; luma auto
matic gain timing allows
adjustment of the luma
AGC tracking speed
0
Slow (TC = 2 sec)
Only has an effect
if LAGC[1:0] is set
to autogain (001,
010, 011, or 100)
0
1
Medium (TC = 1 sec)
1
0
Fast (TC = 0.2 sec)
1
Adaptive
0x30
Luma Gain
Control 2, Luma
Gain2 (LG)
LMG[7:0]/LG[7:0]; luma
manual gain lower eight
bits; see LMG[11:8]/
LG[11:8] for description
x
LMG[11:0] - see the LMG section
LMG[11:0] =- see the LMG section
Min value = 1024d,
Max value = 4095d
0x31
VS/FIELD
Control 1
Reserved
0
1
0
Set to default
HVSTIM; selects where
within a line of video the
VS signal is asserted
0
Start of line relative to HSE
HSE = HSYNC end
1
Start of line relative to HSB
HSB = HSYNC begin
NEWAVMODE; sets the
EAV/SAV mode
0
EAV/SAV codes generated to suit
Analog Devices encoders
1
Manual VS/FIELD position controlled by
Register 0x32, Register 0x33, and
Register 0xE5 to Register 0xEA
Reserved
0
Set to default
0x32
VS/FIELD
Control 2
Reserved
0
1
Set to default
NEWAVMODE bit
must be set high
VSBHE
0
VS goes high in the middle of the
line (even field)
1
VS changes state at the start of the
line (even field)
VSBHO
0
VS goes high in the middle of the
line (odd field)
1
VS changes state at the start of the
line (odd field)
0x33
VS/FIELD
Control 3
Reserved
0
1
0
Set to default
VSEHE
0
VS goes low in the middle of the
line (even field)
NEWAVMODE bit
must be set high
1
VS changes state at the start of the
line (even field)
VSEHO
0
VS goes low in the middle of the line
(odd field)
1
VS changes state at the start of the
line odd field
0x34
HS Position
Control 1
HSE[10:8]; HS end allows
positioning of the HS
output within the
video line
0
HS output ends HSE[10:0] pixels after
the falling edge of HSYNC
Using HSB and
HSE the user can
program the
position and length
of the output
HSYNC
Reserved
0
Set to 0
HSB[10:8]; HS begin
allows positioning of
the HS output within
the video line
0
HS output starts HSB[10:0] pixels
after the falling edge of HSYNC
Reserved
0
Set to 0
0x35
HS Position
Control 2
HSB[7:0]; see Address 0x34,
using HSB[10:0] and
HSE[10:0], users can
program the position
and length of the HS
output signal
0
1
0
0x36
HS Position
Control 3
HSE[7:0]; see Address
0x35 description
0
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