參數(shù)資料
型號(hào)： ADV7180BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 3/116頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 64-LQFP
產(chǎn)品變化通告： ADV7180 Metal Mask Edit 22/Oct/2009
設(shè)計(jì)資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADV7180BSTZ-REELDKR
ADV7180
Data Sheet
Rev. I | Page 100 of 116
To read to and write from the registers in Table 108, the SUB_USR_EN bit (Address 0x0E[5]) must be set to Logic 1.
Table 108. Register Map Descriptions (User Sub Map)1, 2
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x40
Interrupt Configuration 1
INTRQ_OP_SEL[1:0]; interrupt
drive level select
0 0
Open drain
0 1
Drive low when active
1 0
Drive high when active
1 1
Reserved
MPU_STIM_INTRQ; manual
interrupt set mode
0
Manual interrupt mode disabled
1
Manual interrupt mode enabled
Reserved
x
Not used
MV_INTRQ_SEL[1:0];
Macrovision interrupt select
0 0
Reserved
0 1
Pseudo sync only
1 0
Color stripe only
1 1
Pseudo sync or color stripe
INTRQ_DUR_SEL[1:0];
interrupt duration select
0 0
Three XTAL periods
0 1
15 XTAL periods
1 0
63 XTAL periods
1 1
Active until cleared
0x42
Interrupt Status 1
(read only)
SD_LOCK_Q
0
No change
These bits can be cleared
or masked in Register 0x43
and Register 0x44, res-
pectively
1
SD input has caused the decoder to go
from an unlocked state to a locked state
SD_UNLOCK_Q
0
No change
1
SD input has caused the decoder to go
from a locked state to an unlocked state
Reserved
x x x
SD_FR_CHNG_Q
0
No change
1
Denotes a change in the free-run status
MV_PS_CS_Q
0
No change
1
Pseudo sync/color striping detected;
see Register 0x40 MV_INTRQ_SEL[1:0]
for selection
Reserved
x
0x43
Interrupt Clear 1
(write only)
SD_LOCK_CLR
0
Do not clear
1
Clears SD_LOCK_Q bit
SD_UNLOCK_CLR
0
Do not clear
1
Clears SD_UNLOCK_Q bit
Reserved
0 0 0
Not used
SD_FR_CHNG_CLR
0
Do not clear
1
Clears SD_FR_CHNG_Q bit
MV_PS_CS_CLR
0
Do not clear
1
Clears MV_PS_CS_Q bit
Reserved
x
Not used
0x44
Interrupt Mask 1
(read/write)
SD_LOCK_MSK
0
Masks SD_LOCK_Q bit
1
Unmasks SD_LOCK_Q bit
SD_UNLOCK_MSK
0
Masks SD_UNLOCK_Q bit
1
Unmasks SD_UNLOCK_Q bit
Reserved
0 0 0
Not used
SD_FR_CHNG_MSK
0
Masks SD_FR_CHNG_Q bit
1
Unmasks SD_FR_CHNG_Q bit
MV_PS_CS_MSK
0
Masks MV_PS_CS_Q bit
1
Unmasks MV_PS_CS_Q bit
Reserved
x
Not used
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