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| 型號： | ADV7180BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV 64-LQFP |
| 產(chǎn)品變化通告： | ADV7180 Metal Mask Edit 22/Oct/2009 |
| 設(shè)計(jì)資源： | Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 數(shù)碼相機(jī)，手機(jī)，便攜式視頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADV7180BSTZ-REELDKR |
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ADV7180
Data Sheet
Rev. I | Page 102 of 116
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x4A
Interrupt Status 3
(read only)
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
0
No change in SD signal standard
detected at the output
These bits can be cleared
and masked by
Register 0x4B and
Register 0x4C, respectively
1
A change in SD signal standard is
detected at the output
SD_V_LOCK_CHNG_Q
0
No change in SD
VSYNC lock status
1
SD
VSYNC lock status has changed
SD_H_LOCK_CHNG_Q
0
No change in
HSYNC lock status
1
SD
HSYNC lock status has changed
SD_AD_CHNG_Q; SD autodetect
changed
0
No change in AD_RESULT[2:0] bits in
Status 1 register
1
AD_RESULT[2:0] bits in Status 1 register
have changed
SCM_LOCK_CHNG_Q; SECAM lock
0
No change in SECAM lock status
1
SECAM lock status has changed
PAL_SW_LK_CHNG_Q
0
No change in PAL swinging burst
lock status
1
PAL swinging burst lock status has
changed
Reserved
x x
Not used
0x4B
Interrupt Clear 3
(write only)
SD_OP_CHNG_CLR
0
Do not clear
1
Clears SD_OP_CHNG_Q bit
SD_V_LOCK_CHNG_CLR
0
Do not clear
1
Clears SD_V_LOCK_CHNG_Q bit
SD_H_LOCK_CHNG_CLR
0
Do not clear
1
Clears SD_H_LOCK_CHNG_Q bit
SD_AD_CHNG_CLR
0
Do not clear
1
Clears SD_AD_CHNG_Q bit
SCM_LOCK_CHNG_CLR
0
Do not clear
1
Clears SCM_LOCK_CHNG_Q bit
PAL_SW_LK_CHNG_CLR
0
Do not clear
1
Clears PAL_SW_LK_CHNG_Q bit
Reserved
x x
Not used
0x4C
Interrupt Mask 3
(read/write)
SD_OP_CHNG_MSK
0
Masks SD_OP_CHNG_Q bit
1
Unmasks SD_OP_CHNG_Q bit
SD_V_LOCK_CHNG_MSK
0
Masks SD_V_LOCK_CHNG_Q bit
1
Unmasks SD_V_LOCK_CHNG_Q bit
SD_H_LOCK_CHNG_MSK
0
Masks SD_H_LOCK_CHNG_Q bit
1
Unmasks SD_H_LOCK_CHNG_Q bit
SD_AD_CHNG_MSK
0
Masks SD_AD_CHNG_Q bit
1
Unmasks SD_AD_CHNG_Q bit
SCM_LOCK_CHNG_MSK
0
Masks SCM_LOCK_CHNG_Q bit
1
Unmasks SCM_LOCK_CHNG_Q bit
PAL_SW_LK_CHNG_MSK
0
Masks PAL_SW_LK_CHNG_Q bit
1
Unmasks PAL_SW_LK_CHNG_Q bit
Reserved
x x
Not used
0x4E
Interrupt Status 4 (read only) VDP_CCAPD_Q
0
Closed captioning not detected
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively; note that an
interrupt in Register 0x4E
for the CCAP, Gemstar,
CGMS, WSS, VPS, PDC,
UTC, and VITC data uses
the VDP data slicer
1
Closed captioning detected
Reserved
x
VDP_CGMS_WSS_CHNGD_Q; see
0x9C Bit 4 of user sub map to determine
whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
0
CGMS/WSS data is not changed/
not available
1
CGMS/WSS data is changed/available
Reserved
x
VDP_GS_VPS_PDC_UTC_CHNG_Q;
see 0x9C Bit 5 of User Sub Map to deter-
mine whether interrupt is issued for a
change in detected data or for when
data is detected regardless of content
0
Gemstar/PDC/VPS/UTC data is not
changed/not available
1
Gemstar/PDC/VPS/UTC data is
changed/available
Reserved
x
VDP_VITC_Q
0
VITC data is not available in the VDP
1
VITC data is available in the VDP
Reserved
x
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