參數(shù)資料
型號(hào): AGL10005-FFG144I
元件分類(lèi): FPGA
英文描述: FPGA, 1000000 GATES, 250 MHz, PBGA144
封裝: 13 X 13 MM, 1 MM PITCH, FBGA-144
文件頁(yè)數(shù): 170/204頁(yè)
文件大?。?/td> 2800K
代理商: AGL10005-FFG144I
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)當(dāng)前第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 54
Advanced v0.1
I/O State in Flash*Freeze Mode
When the device enters Flash*Freeze mode, I/Os will
become tristated. If the weak pull-up or pull-down
feature is used, the I/Os will maintain the configured
weak pull-up or pull-down status. This feature enables
the design to set the I/O state to a certain level that is
determined by the pull-up/-down configuration. For
example, use the output buffer and enable weak pull-
down to drive a signal LOW to an external component
while the IGLOO device is in Flash*Freeze mode.
Table 2-30 shows the I/O pad state based on the
configuration and buffer type.
Note that configuring weak pull-up or pull-down for the
FF pin is not allowed.
Flash*Freeze Mode Design Considerations
Entering Flash*Freeze Mode
The device was designed and optimized to enter
Flash*Freeze mode only when power supplies are
stable. If the device is being powered up while the FF
pin is asserted (Flash*Freeze mode type 1) or both FF
pin and LSICC signal are asserted (Flash*Freeze mode
type 2), the device is expected to enter Flash*Freeze
mode within 5 s after the I/Os and FPGA core have
reached their activation levels.
If the device is already powered up and then the
FF
pin
is
asserted,
the
device
will
enter
Flash*Freeze mode within 1 s (type 1). In
Flash*Freeze mode type 2 operation, entering
Flash*Freeze mode is done within 1 s after both
FF pin and LSICC signal are asserted. Exiting
Flash*Freeze mode is done within 1 s after
deasserting the FF pin only.
If an embedded PLL is used, entering Flash*Freeze
mode will automatically power down the PLL.
The PLL output clocks will stop toggling within
1 s after the assertion of the FF pin in type 1, or
after both FF pin and LSICC signal are asserted in
type 2. At the same time, I/Os will transition into
the state specified in Table 2-30. The user design
must ensure it is safe to enter Flash*Freeze mode.
During Flash*Freeze Mode
Inputs and input clocks to the FPGA can toggle
without any impact on static power consumption,
assuming weak pull-up or pull-down is not
selected.
If weak pull-up or pull-down is selected and the
input is driven to the opposite direction, power
dissipation will occur.
Any
toggling
signals
will
be
charging
and
discharging the package pin capacitance.
Outputs will be tristated, and the output of the
input or bidirectional buffer tied to the internal
logic will be set to logic 1. Refer to Table 2-30 for
more information.
JTAG operations such as JTAG commands, JTAG
bypass, programming and authentication cannot
be executed. The device must exit Flash*Freeze
mode before JTAG commands can be sent.
The FF pin must be externally driven (deasserted)
for the device to stay in Flash*Freeze mode.
The FF pin is still active; i.e., the pin is used to exit
Flash*Freeze mode when deasserted.
Table 2-30 Flash*Freeze Mode (type 1 and type 2)—I/O Pad State
Buffer Type
Internal Weak Pull-Up/-Down
I/O Pad State in Flash*Freeze Mode
Input
Enabled
Weak pull-up/pull-down*
Disabled
Tristate*
Output
Enabled
Weak pull-up/pull-down
Disabled
Tristate
Tristate output buffer
E = 0 (tristate)
N/A
Tristate
E = 1 (output)
N/A
Tristate
Bidirectional
E = 0 (input)
Enabled
Weak pull-up/pull-down*
Disabled
Tristate*
E = 1 (output)
Enabled
Weak pull-up/pull-down
Disabled
Tristate
Note: *Internal core logic driven by this input buffer will be tied to logic 1 as long as the device is in Flash*Freeze mode.
相關(guān)PDF資料
PDF描述
AGL10005-FFG144 FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFG256I FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFG256 FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFG484I FPGA, 1000000 GATES, 250 MHz, PBGA484
AGL10005-FFG484 FPGA, 1000000 GATES, 250 MHz, PBGA484
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGL1000V2-CS144 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144ES 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144I 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144PP 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS281 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA(27X27)