參數(shù)資料
型號： AGLE600V5-FFGG484C
元件分類： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
文件頁數(shù)： 109/156頁
文件大小： 5023K
代理商： AGLE600V5-FFGG484C
IGLOOe DC and Switching Characteristics
2- 42
Advance v0.3
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI
Bus applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable
path characterization are described in Figure 2-12.
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in Table 2-62.
Table 2-61 Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
VIH
VOL
VOH
IOL
IO
H
IOSH
IOSL
IIL
IIH
Drive Strength
Min.,
V
Max.,
V
Min.,
V
Max.,
V
Max.,
V
Min.,
V
m
A
m
AMax., mA1 Max., mA1
A
2
A
2
Per PCI
specification
Per PCI curves
10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-12 AC Loading
Test Point
Enable Path
R to V
for t /t /t
CCI
LZ ZL
ZLS
10 pF for t
/t
/t /t
ZH ZHS
ZLS
ZL
5 pF for tHZ /tLZ
R to GND for t
/t
HZ
ZH
ZHS
R = 1 k
Test Point
Datapath
R = 25
R to VCCI for tDP (F)
R to GND for tDP (R)
Table 2-62 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point*
(V)
VREF (typ.) (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–10
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
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