參數(shù)資料
型號: AGLE600V5-FFGG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
文件頁數(shù): 79/156頁
文件大小: 5023K
代理商: AGLE600V5-FFGG484C
IGLOOe DC and Switching Characteristics
Ad vance v0.3
2-15
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.
If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.
Below are some examples:
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of
the clock frequency.
The average toggle rate of an 8-bit counter is 25%:
Bit 0 (LSB) = 100%
Bit 1
= 50%
Bit 2
= 25%
–…
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled.
When nontristate output buffers are used, the enable rate should be 100%.
Table 2-18 Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
α
1
Toggle rate of VersaTile outputs
10%
α
2
I/O buffer toggle rate
10%
Table 2-19 Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
β
1
I/O output buffer enable rate
100%
β
2
RAM enable rate for read operations
12.5%
β
3
RAM enable rate for write operations
12.5%
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