參數資料
型號: AGLE600V5-FFGG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
文件頁數: 122/156頁
文件大?。?/td> 5023K
代理商: AGLE600V5-FFGG484C
IGLOOe DC and Switching Characteristics
2- 54
Advance v0.3
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-85 Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V
Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
15 mA3
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.4
VCCI – 0.4 15 15
66
55
10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Figure 2-18 AC Loading
Table 2-86 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.750.750.75
20
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
20 pF
25
HSTL
Class II
VTT
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