參數(shù)資料
型號(hào)： AGLN250V2-QN100
元件分類： FPGA
英文描述： FPGA, PBCC100
封裝： 8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, QFN-100
文件頁(yè)數(shù)： 1/114頁(yè)
文件大?。?/td> 3991K
代理商： AGLN250V2-QN100
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December 2008
I
2008 Actel Corporation
IGLOO nano Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
Small Footprint Packages
As Small as 3x3 mm in Size
Wide Range of Features
10 k to 250 k System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 71 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock to Secure FPGA Contents
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Selectable Schmitt Trigger Inputs
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL
Up to Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except × 18 organization)
Enhanced Commercial Temperature Range
–20°C to +70°C
AGLN030 and smaller devices do not support this feature.
IGLOO nano Devices
AGLN010
AGLN015
AGLN020
AGLN030 1
AGLN060
AGLN125
AGLN250
System Gates
10 k
15 k
20 k
30 k
60 k
125 k
250 k
Typical Equivalent Macrocells
86
128
172
256
512
1,024
2,048
VersaTiles (D-flip-flops)
260
384
520
768
1,536
3,072
6,144
Flash*Freeze Mode (typical, W)
2
4
5
10
16
24
RAM kbits (1,024 bits)2
–
18
36
4,608-Bit Blocks2
––
–
4
8
FlashROM Bits
1 k
Secure (AES) ISP 2
––
–
Yes
Integrated PLL in CCCs2
––
–
1
VersaNet Globals3
4
6
18
I/O Banks
23
3
2
4
Maximum User I/Os
34
49
52
81
71
68
Maximum User I/Os (Known Good Die)
34
–
52
83
71
68
Package Pins
UC/CS
QFN
VQFP
UC36
QN48
QN68
UC81, CS81
QN68
UC81, CS81
QN48, QN68
VQ100
CS81
QN100
VQ100
CS81
QN100
VQ100
CS81
QN100
VQ100
Notes:
1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer
2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this
feature
.
3. Six chip (main) and three quadrant global networks are available for AGLN060 and above.
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe handbooks.
Advance v0.4
相關(guān)PDF資料
PDF描述
AGLN250V2-QNG100I FPGA, PBCC100
AGLN250V2-QNG100 FPGA, PBCC100
AGLN250V2-ZFVQ100 FPGA, PQFP100
AGLN250V2-ZFVQG100 FPGA, PQFP100
AGLN015V2-FQN68 FPGA, PQCC68
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLN250V2-QNG100I 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO FAMILY 250K GATES 130NM (CMOS) TECHNOLOGY 1. - Trays
AGLN250V2-VQ100 功能描述:IC FPGA NANO 1KB 250K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN250V2-VQ100I 功能描述:IC FPGA NANO 1KB 250K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN250V2-VQG100 功能描述:IC FPGA 250K 1.2-1.5V 100VTQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
AGLN250V2-VQG100I 功能描述:IC FPGA NANO 1KB 250K 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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