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參數(shù)資料
| 型號： | AGLP125V5-CSG289I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| 封裝： | 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289 |
| 文件頁數(shù)： | 29/128頁 |
| 文件大小： | 4383K |
| 代理商： | AGLP125V5-CSG289I |
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Datasheet Information
4- 4
R ev isio n 1 1
Revision 4 (Jul 2008)
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
Revision 3 (Jun 2008)
DC and Switching
Characteristics
Advance v0.2
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
N/A
Table note 3 was updated in Table 2-2 Recommended Operating Conditions1,2
to add the sentence, "VCCI should be at the same voltage within a given I/O
bank." References to table notes 5, 6, 7, and 8 were added. Reference to table
note 3 was removed from VPUMP Operation and placed next to VCC.
Table 2-4 Overshoot and Undershoot Limits 1 was revised to remove "as
measured on quiet I/Os" from the title. Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
The table note for Table 2-9 Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do
not include I/O static contribution.
The table note for Table 2-10 Quiescent Supply Current (IDD) Characteristics,
statement that values do not include I/O static contribution.
The table note for Table 2-11 Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Shutdown Mode was updated to remove the statement that values
do not include I/O static contribution.
I/O Software Settings1 were updated to remove static power. The table notes
were updated to reflect that power was measured on VCCI. Table note 2 was
the Static Power Consumption in IGLOO PLUS Devices were updated to change
the definition for PDC5 from bank static power to bank quiescent power. Table
subtitles were added for Table 2-16 Different Components Contributing to the
2-11,
The "Total Static Power Consumption—PSTAT" section was revised.
Packaging v1.3
The "281-Pin CSP" package drawing is new.
The "281-Pin CSP" table for the AGLP125 device is new.
Revision
Changes
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLP125V5-CSG289 | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP125V5CS281I | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| AGLP125V5CS281 | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| AGLP125V5CS289I | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP125V5CS289 | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP125-V5CSG289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-FCS281 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 125K GATES 1024 CELLS 130NM 1.5V 281CSP - Trays |
| AGLP125-V5FCS289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-FCS289 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 125K GATES 1024 CELLS 130NM 1.5V 289CSP - Trays |
| AGLP125-V5FCS289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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