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參數(shù)資料
| 型號： | AK4356AVQ |
| 英文描述： | D/A CONVERTER |
| 中文描述： | D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 226K |
| 代理商： | AK4356AVQ |
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ASAHI KASEI
[AK4356A]
MS0035-E-00
2000/7
- 17 -
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Zero detection
The AK4356A has channel-independent zeros detect function. When the input data at each channel is continuously zero
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of all channels go to “H”. DZF pins
of all channels go to “L” 4/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of all channels go to “H”
only when the input data at all channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of all channels are always “L” (except for the case of RSTN = “0”).
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Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-
∞
during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting
the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE
Attenuation
DZF
1024/fs
(1)
0dB
-
∞
AOUT
1024/fs
8192/fs
GD
(2)
GD
(3)
(4)
Notes:
(1) The output signal is attenuated by -
∞
during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input have the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft mute and zero detection
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System Reset
The AK4356A should be reset once by bringing PDN = “L” upon power-up. The AK4356A is powered up and the
internal timing starts clocking by LRCK “
↑
” after exiting reset and power down state by MCLK. The AK4356A is in the
power-down mode until MCLK and LRCK are input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4356VQ | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4357 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 6ch DAC with DSD Input |
| AK4357VQ | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 6ch DAC with DSD Input |
| AK4358 | 制造商:AKM 制造商全稱:AKM 功能描述:digital audio interface that can interface with digital audio systems via opt-connector or RCA connector |
| AK4358_06 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 8ch DAC with DSD Input |
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