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參數(shù)資料
| 型號： | AK4356AVQ |
| 英文描述： | D/A CONVERTER |
| 中文描述： | D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大小： | 226K |
| 代理商： | AK4356AVQ |
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ASAHI KASEI
[AK4356A]
MS0035-E-00
2000/7
- 20 -
n
Serial Control Interface
The AK4356A can control its functions via both pins and registers. CKS2-0, DIF2-0, DFS0, DZFE and SMUTE pins are
ORed with their registers.
Internal registers may be written to the 3 wire uP interface pins: CSN, CCLK & CDTI. The data on this interface consists
of Chip address (2bits, CAD0/1), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first,
8bits). Address and data is clocked in on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN.
The clock speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access.
The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their
default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is
not be initialized.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0:Chip Address (C1=CAD1, C0=CAD0)
R/W:
Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0:Control Data
Figure 7. Control I/F Timing
Function
Double Speed
4 times Speed
De-emphasis
DZFE
DZFM
SMUTE
Attenuator
Slow roll-off response
Table 6. Function Table (O: Supported, X: Not supported)
Pin set-up
O
X
X
O
X
O
X
X
Register set-up
O
O
O
O
O
O
O
O
Note: Writing to control register is inhibited when PDN = “L” or the MCLK is not fed.
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