參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 11/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
5-3. Output Signal Timing Diagram ( CCIR625 Component input )
The VERTICAL Sync signal, FIELD signal and FRAME signal timing relationships are shown. The logical state of HSYNC/VSYNC/FIELD/FRAME can be altered by using register settings.
Either VSYNC or VD output signals are available on the VSYNC output pin, depending upon the register setting. The FIELD output and the FRAME output signals change state on the
rising edge of the CSYNC, prior to the 0.5H delay period that is controlled by the output control register. Field/FRAME output timings are shown on pages 20 and 21.
FRAME
(Low)
HSYNC
VSYNC
VD
FIELD
EVEN
ODD
HSYNC
VSYNC
VD
FRAME
FIELD
EVEN
ODD
FRAME
HSYNC
VSYNC
EVEN
ODD
FIELD
HSYNC
VSYNC
VD
EVEN
ODD
FIELD
FRAME
(High
VD
CSYNC
62
1
2
3
4
5
6
8
7
CSYNC
31
30
31
32
30
32
CSYNC
1
62
2
3
4
5
6
8
7
CSYNC
31
30
31
32
30
32
62
Rev.0
19
2002/0
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