參數(shù)資料
型號: AK8850
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: NTSC Digital Video Decoder
中文描述: NTSC制式數(shù)字視頻解碼器
文件頁數(shù): 77/99頁
文件大?。?/td> 1757K
代理商: AK8850
ASAHI KASEI
[AK8850]
CLAMP TIMING 2 CONTROL REGISTER ( R / W ) [ SUB ADDRESS 0x0C ]
This register sets the Pedestal Clamp timing.
The timing of the Clamp Timing Pulse generation and its pulse width can be adjusted.
Sub Address 0x0C
Default Value :0x1C
For timing diagram,refer to the SYNC-Separation description in the Clamp section. Reserved bits must be set to “ 0 “.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SLCLV1
SLCLV0
PCLPWIDTH0
PCLPSTAT2
PCLPSTAT1
PCLPSTAT0
PCLPWIDTH2
PCLPWIDTH1
Default Value
0
1
CLAMP Timing 2 Control Register
Register Name
R/W
Definition
bit 0
PCLPSTAT0
PCLPSTAT2
Pedestal Clamp Start timing0 bit
Pedestal Clamp Start timing2
bit
R/W
Setting the start position of pedestal clamp
pulse.
default value is
PCLPSTA2 : PCLPSTA0 = 100
[PCLPSTAT2 PCLPSTAT0]
001 : 126 clks (4.65usec) later
010 : 132 clks (4.88usec) later
011 : 140 clks (5.18usec) later
100 : 148 clks (5.48usec) later
101 : 156 clks (5.77usec) later
110 : 164 clks (6.07usec) later
111 : 172 clks (6.36usec) later
bit 3
bit 5
PCLPWIDTH0
PCLPWIDTH3
Pedestal Clamp Pulse Width0
Setting the pedestal clamp timing pulse width.
Default value is
PCLPWIDTH2 : PCLPWIDTH0 = 011
[PCLPWIDTH3 PCLPWIDTH0]
000 : 16 clks (592 nsec)
BIT
000 : 118 clks (4.37usec) later
bit 2
1clk is about 37[nsec]
Pedestal Clamp Pulse Width3
bit
100 : 40 clks (1.48 usec)
111 : 52 clks (1.92 usec)
001 : 24 clks (888 nsec)
R/W
010 : 28 clks (1.04 usec)
011 : 32 clks (1.18 usec)
101 : 44 clks (1.63 usec)
110 : 48 clks (1.78 usec)
Setting the slice level
Default value is 00
[SLCLV1:SLCLV0] =
SLCLV0
bit 6
00 :Sliced 1/4 level above the synctip
Slice Level Control bit
R/W
01 :Sliced 1/2 level above the synctip
SLCLV1
bit 7
10 :Prohibit to set
11: Sliced 3/8 level above the synctip
Rev.0
79
2003/01
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