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參數(shù)資料
| 型號： | AK8850 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | NTSC Digital Video Decoder |
| 中文描述： | NTSC制式數(shù)字視頻解碼器 |
| 文件頁數(shù)： | 25/99頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | AK8850 |
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ASAHI KASEI
[AK8850]
( 1-3 ) CLAMP PULSE MASK FUNCTION
To avoid mis-clamping, the SYNCDET signal is masked outside the SYNC signal period. The masking period is from the
rising edge of the SYNCDET signal to 1536 clock periods ( 1 clock = 37 ns ). During this period, no SYNCDET signal is
generated ( refer to the timing diagram below ).
This pulse mask is reset via register programming ( refer to item 1-6-5 ).
Input video
SYNCDET
CLPMASK
1536 clks
( 1-4 ) EXTERNAL CLAMP TIMING INPUT VIA EXTCLP PIN
It is possible to input an external clamp timing pulse via the EXTCLP pin by setting the INCLPTMG-bit and
[ FBCLPTMG1 : FBCLPTMG0 ]-bits of the [ CLAMP CONTROL REGISTER ]. For further register settings, please refer
to item ( 1-6 ) SYNC SEPARATION REGISTER RELATED DESCRIPTION.
( 1-5 ) CLAMP TIMING PULSE MONITOR FUNCTION
It is possible to monitor the internal clamp timing through the EXTCLP pin only when no external clamp timing is used.
Output signals monitored on EXTCLP pin are SYNC-TIP clamp timing pulse, Pedestal clamp timing pulse and
SYNCDET signal. The target signal is selected by [ EXTCLP1 : EXTCLP0 ]-bit of the [ CLAMP TIMING 1 CONTROL
REGISTER ].
( 1-6 ) SYNC-SEPARATION RELATED REGISTER DESCRIPTION
Sync-separation and Clamp pulse related registers are [ INPUT SIGNAL SELECT REGISTER ], [ CLAMP CONTROL
REGISTER ], [ CLAMP TIMING 1 CONTROL REGISTER ] and [ CLAMP TIMING 2 CONTROL REGISTER ].
Select Sync-separation signal is done using the [ INPUT SIGNAL SELECT REGISTER ].
[Input Signal Select Register]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
SYNCIN1
SYNCIN0
INSEL3
INSEL2
INSEL1
INSEL0
Default Value
0
1
0
1
[ SYNCIN 1 : SYNCIN 0 ]-bit selects one of the SYNC 1 / 2 / 3 input signals to generate the clamp pulse.
[SYNCIN1:SYNCIN0]
(bit5:bit4)
Target video signal for Sync separation
00
No Input
01
Video signal input from SYNC1 pin
10
Video signal input from SYNC2 pin
11
Video signal input from SYNC3 pin
Rev.0
31
2002/01
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