- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366405 > AM29DL642G70MDI (ADVANCED MICRO DEVICES INC) 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo PDF資料下載
參數(shù)資料
| 型號： | AM29DL642G70MDI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| 中文描述： | 8M X 16 FLASH 3.3V PROM MODULE, 70 ns, PBGA63 |
| 封裝： | 10.95 X 11.95 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數(shù)： | 11/54頁 |
| 文件大?。?/td> | 828K |
| 代理商： | AM29DL642G70MDI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
June 10, 2005
Am29DL642G
9
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29DL642G Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at the
same time.
4. If WP#/ACC = V
IL
, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V
IH
, protection on sectors 0, 1, 140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = V
HH
, all sectors will be unprotected.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC
Read-Only Operations
table for timing
specifications and to
Figure 13
for the timing diagram.
I
CC1
in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# (or CE2#) to V
IL
, and OE# to V
IH
.
Operation
CE#
(Note 3)
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 1)
DQ15–
DQ0
Read
L
L
H
H
L/H
A
IN
D
OUT
Write
L
H
L
H
(Note 4)
A
IN
D
IN
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
L/H
X
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
Reset
X
X
X
L
L/H
X
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
L/H
SA, A6 = L,
A1 = H, A0 = L
D
IN
Sector Unprotect (Note 2)
L
H
L
V
ID
(Note 4)
SA, A6 = H,
A1 = H, A0 = L
D
IN
Temporary Sector Unprotect
X
X
X
V
ID
(Note 4)
A
IN
D
IN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29DL642G90I | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| AM29DL642G90MDI | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| AM29DL800BB120ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BT120WBK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BT70ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29DL800BB-120WBD | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 8Mbit 1M/512K x 8bit/16bit 120ns 48-Pin FBGA |
| AM29DL800BB-70SI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 8MBIT 1MX8/512KX16 70NS 44SOIC - Trays |
| AM29DL800BB-90EI | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 8Mbit 1M/512K x 8bit/16bit 90ns 48-Pin TSOP |
| AM29DL800BT-120EC | 制造商:Spansion 功能描述:SPZAM29DL800BT-120EC TB 120n EOL160610 |
| AM29DL800BT-120WBC | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。