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參數(shù)資料
| 型號(hào)： | AM29DL642G70MDI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| 中文描述： | 8M X 16 FLASH 3.3V PROM MODULE, 70 ns, PBGA63 |
| 封裝： | 10.95 X 11.95 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數(shù)： | 43/54頁 |
| 文件大?。?/td> | 828K |
| 代理商： | AM29DL642G70MDI |
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June 10, 2005
Am29DL642G
41
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter
70
90
JEDEC
Std
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
90
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
40
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
40
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# or CE#2 Setup Time
Min
0
ns
t
WHEH
t
CH
CE# or CE#2 Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 2)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
t
VCS
V
CC
Setup Time (Note 1)
Min
50
μs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
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