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參數(shù)資料
| 型號： | AM29DL642G |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| 中文描述： | 128兆位（8米× 16位）的CMOS 3.0伏，只有同時讀/寫閃存?zhèn)渫?/td> |
| 文件頁數(shù)： | 41/54頁 |
| 文件大?。?/td> | 828K |
| 代理商： | AM29DL642G |
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June 10, 2005
Am29DL642G
39
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See
Figure 11
and Table 15 for test specifications
3. CE# and CE2# must not be driven low simultaneously.
4. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE# high to
the data bus driven to V
CC
/2 is taken as t
DF
.
Parameter
Description
Test Setup
70
90
JEDEC
Std.
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
70
90
ns
t
AVQV
t
ACC
Address to Output Delay (Note 3)
CE# or CE2#,
OE# = V
IL
Max
70
90
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
70
90
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 4)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 4)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time (Note
1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE# or CE2#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 13.
Read Operation Timings
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