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參數(shù)資料
| 型號： | AM29LV001BB-70ED |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | Flash Memory IC; Memory Size:1Mbit; Package/Case:48-TSOP; Supply Voltage Max:3V; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Access Time, Tacc:70nS; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 128K X 8 FLASH 3V PROM, 70 ns, PDSO32 |
| 封裝： | LEAD FREE, MO-142BBD, TSOP-32 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 841K |
| 代理商： | AM29LV001BB-70ED |
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Am29LV001B
21557F4 May 5, 2006
DATA S H EET
GENERAL DESCRIPTION
The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV001B has a boot sector architecture.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7-DQ0.
All read, erase, and program operations are accomplished
using only a single power supply. The device can also be
programmed in standard EPROM programmers.
The standard Am29LV001B offers access times of 45,
55, 70, and 90 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus contention,
the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single power supply (2.7 V–3.6V)
for both read and write functions. Internally generated and
regulated voltages are provided for the program and
erase operations.
The Am29LV001B is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically
times the program pulse widths and verifies proper cell
margin. The Unlock Bypass mode facilitates faster pro-
gramming times by requiring only two write cycles to
program data instead of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm—
an internal algorithm that automatically preprograms the
array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any com-
bination of the sectors of memory. This can be achieved
in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in
progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses are stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The
device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV002BB-120ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV002BT-70EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV002BT-90ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV002BT-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV004BB-120ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV001BB-90JD | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 1MBIT 128KX8 90NS 32PLCC - Rail/Tube |
| AM29LV001BT-55ED | 制造商:Spansion 功能描述:1M (128KX8) 3V, BOOT BLOCK, TOP, TSOP32, COM - Trays |
| AM29LV002BB-90EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV002BT-90EF | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 2Mbit 256K x 8bit 90ns 40-Pin TSOP |
| AM29LV002BT-90EI\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
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