參數(shù)資料
型號(hào)： AM29LV001BB-70ED
廠商： SPANSION LLC
元件分類： PROM
英文描述： Flash Memory IC; Memory Size:1Mbit; Package/Case:48-TSOP; Supply Voltage Max:3V; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Access Time, Tacc:70nS; Series:AM29 RoHS Compliant: Yes
中文描述： 128K X 8 FLASH 3V PROM, 70 ns, PDSO32
封裝： LEAD FREE, MO-142BBD, TSOP-32
文件頁(yè)數(shù)： 6/43頁(yè)
文件大?。?/td> 841K
代理商： AM29LV001BB-70ED
12
Am29LV001B
21557F4 May 5, 2006
DATA S H EET
Figure 2.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 on page 17
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until
VCC is greater than VLKO. The system must provide
the proper signals to the control pins to prevent unin-
tentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
相關(guān)PDF資料
PDF描述
AM29LV002BB-120ED Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes
AM29LV002BT-70EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes
AM29LV002BT-90ED Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
AM29LV002BT-90EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
AM29LV004BB-120ED Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes
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