參數(shù)資料
型號(hào): AM29LV008BT-90ED
廠商: SPANSION LLC
元件分類: PROM
英文描述: Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
中文描述: 1M X 8 FLASH 3V PROM, 90 ns, PDSO40
封裝: LEAD FREE, MO-142BCD, TSOP-40
文件頁(yè)數(shù): 35/41頁(yè)
文件大?。?/td> 738K
代理商: AM29LV008BT-90ED
40
Am29LV008B
21524D7 February 24, 2009
D A TA SH EET
REVISION SUMMARY
Revision A (October 1997)
First release.
Revision B (January 1998)
Distinctive Characteristics
Changed typical read and program/erase current
specifications.
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Figure of In-System Sector Protect/Unprotect
Algorithm
Corrected A6 to 0, Changed wait specification to 150 s
on sector protect and 15 ms on sector unprotect.
DC Characteristics
Changed typical read and program/erase current
specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:
Changed tCP to 35 ns for 70R, 80, and 90 speed options.
Erase and Programming Performance
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Revision B+1 (March 1998)
Figure of In-System Sector Protect/Unprotect
Algorithms
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect another
sector?” back to setting up the next sector address.
DC Characteristics
Changed Note 1 to indicate that OE# is at VIH for the
listed current.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the notes refer-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Corrected the note reference for tVCS.
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Figure 21, Sector Protect/Unprotect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cycles.
Revision C (January 1999)
Global
Updated for CS39S process technology.
Distinctive Characteristics
Added:
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
DC Characteristics—CMOS Compatible
ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “Maximum
ICC specifications are tested with VCC = VCCmax”.
ICC3, ICC4: Deleted VCC = VCCmax.
Revision D (November 19, 1999)
AC Characteristics—Figure 15. Program
Operations Timing and Figure 16. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision D+1 (August 14, 2000)
Global
Deleted 80 ns speed option.
Ordering Information
Deleted burn-in option.
Revision D+2 (November 10, 2000)
Command Definitions
Reset Command: Deleted reference to Figure 14, RE-
SET# Timings, which is only applicable to the hardware
reset function.
Revision D+3 (June 11, 2004)
Ordering Information
Added Pb-Free OPNs.
Revision D4 (February 21, 2006)
Global
Removed Reverse TSOP option.
Revision D5 (September 12, 2006)
Erase and Program Operations table
Changed tBUSY to a maximum specification.
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AM29LV008BT-90EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
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