參數(shù)資料
型號(hào)： AM29LV081B120EE
廠商： Advanced Micro Devices, Inc.
英文描述： 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
中文描述： 8兆位（1米× 8位）的CMOS 3.0伏特，只有統(tǒng)一部門(mén)閃存
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 438K
代理商： AM29LV081B120EE
21525D6
October 12, 2006
Am29LV081B
13
D AT A S H E E T
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. The device then re-
turns to reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a
hardware
reset
during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table 4 for program command sequence.
Figure 3. Program Operation
相關(guān)PDF資料
PDF描述
AM29LV081B120EF 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
AM29LV081B120EI 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
AM29LV081B120EK 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
AM29LV081B-70ED 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
AM29LV081B-70EF 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29LV081B-70EC 制造商:Advanced Micro Devices 功能描述: 制造商:Atmel Corporation 功能描述:
AM29LV081B-70ED 制造商:Spansion 功能描述:IC FLASH MEMORY PARALLEL 制造商:Advanced Micro Devices 功能描述:NOR Flash, 1M x 8, 40 Pin, Plastic, TSSOP
AM29LV081B-70ED 制造商:Spansion 功能描述:Flash Memory IC
AM29LV081B-90EC 制造商:ADV-MICRO-DEV 功能描述:
AM29LV081B-90ED 制造商:Spansion 功能描述:Flash Memory IC 制造商:Advanced Micro Devices 功能描述:1M X 8 FLASH 3V PROM, 90 ns, PDSO40
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