參數(shù)資料
型號(hào)： AM29LV800DT-120ED
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： PROM
英文描述： Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1800pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: P Failure Rate
中文描述： 512K X 16 FLASH 3V PROM, 120 ns, PDSO48
封裝： LEAD FREE, MO-142DD, TSOP-48
文件頁(yè)數(shù)： 19/51頁(yè)
文件大?。?/td> 1628K
代理商： AM29LV800DT-120ED
January 21, 2005 Am29LV800D_00_A4_E
Am29LV800D
17
P R E L I M I N A R Y
Hardware Data Protection
The command sequence requirement of unlock
cycles for programming or erasing provides data
protection against inadvertent writes (refer to
Table 5 for command definitions). In addition,
the following hardware data protection mea-
sures prevent accidental erasure or program-
ming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and power-down transitions, or from
system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not
accept any write cycles. This protects data
during V
CC
power-up and power-down. The
command register and all internal pro-
gram/erase circuits are disabled, and the device
resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide
Command Definitions
Writing specific address and data commands or
sequences into the command register initiates
device operations. Table 5 defines the valid reg-
ister command sequences. Writing
incorrect
address and data values
or writing them in
the
improper sequence
resets the device to
reading array data.
the proper signals to the control pins to prevent
unintentional writes when V
CC
is greater than
V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE# = V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate
a write cycle, CE# and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during
power up, the device does not accept com-
mands on the rising edge of WE#. The internal
state machine is automatically reset to reading
array data on power-up.
All addresses are latched on the falling edge of
WE# or CE#, whichever happens later. All data
is latched on the rising edge of WE# or CE#,
whichever happens first. Refer to the appro-
priate timing diagrams in the “AC Characteris-
tics” section.
Reading Array Data
The device is automatically set to reading array
data after device power-up. No commands are
required to retrieve data. The device is also
ready to read array data after completing an
Embedded Program or Embedded Erase algo-
rithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend
mode. The system can read array data using the
standard read timings, except that if it reads at
an address within erase-suspended sectors, the
device outputs status data. After completing a
programming operation in the Erase Suspend
mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must
issue the reset command to
re-enable the device for reading array data if
DQ5 goes high, or while in the autoselect mode.
See the “Reset Command” section, next.
See also “Requirements for Reading Array Data”
in the “Device Bus Operations” section for more
information. The Read Operations table provides
the read parameters, and Figure 1 shows the
timing diagram.
Reset Command
Writing the reset command to the device resets
the device to reading array data. Address bits
are don’t care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to
reading array data. Once erasure begins, how-
ever, the device ignores reset commands until
the operation is complete.
The reset command may be written between the
sequence cycles in a program command
sequence before programming begins. This
resets the device to reading array data (also
applies to programming in Erase Suspend
mode). Once programming begins, however, the
device ignores reset commands until the opera-
tion is complete.
The reset command may be written between the
sequence cycles in an autoselect command
sequence. Once in the autoselect mode, the
reset command
must
be written to return to
reading array data (also applies to autoselect
during Erase Suspend).
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