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| 型號： | AM29SL400CB100RED |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic 12-Stage Binary Counter 16-CDIP -55 to 125 |
| 中文描述： | 256K X 16 FLASH 1.8V PROM, 100 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 11/44頁 |
| 文件大?。?/td> | 945K |
| 代理商： | AM29SL400CB100RED |
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March 3, 2005
9
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of
the device bus operations, which are initiated
through the internal command register. The com-
mand register itself does not occupy any addressable
memory location. The register is composed of
latches that store the commands, along with the ad-
dress and data information needed to execute the
command. The contents of the register serve as in-
puts to the internal state machine. The state ma-
chine outputs dictate the function of the device.
Table 1
lists the device bus operations, the inputs
and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29SL400C Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 10
±
1.0 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Addresses are A17:A0 in word mode (BYTE# = V
IH
), A17:A-1 in byte mode (BYTE# = V
IL
).
2.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configu-
ration. If the BYTE# pin is set at logic ‘1’, the device
is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in
byte configuration, and only data I/O pins DQ0–DQ7
are active and controlled by CE# and OE#. The data
I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin
is used as an input for the LSB (A-1) address func-
tion.
Requirements for Reading Array Data
To read array data from the outputs, the system
must drive the CE# and OE# pins to V
IL
. CE# is the
power control and selects the device. OE# is the out-
put control and gates array data to the output pins.
WE# should remain at V
IH
. The BYTE# pin deter-
mines whether the device outputs array data in
words or bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See
Reading Array Data on page 14
for more infor-
mation. Refer to the AC Read Operations table for
timing specifications and to
Figure 14 on page 28
for
the timing diagram. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Operation
CE#
OE#
WE
#
RESET#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read
L
L
H
H
A
IN
D
OUT
D
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
L
H
L
H
A
IN
D
IN
D
IN
Standby
V
CC
±
0.2 V
X
X
V
CC
±
0.2 V
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
D
IN
X
X
Sector Unprotect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
A
IN
D
IN
D
IN
High-Z
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