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參數(shù)資料
| 型號： | AM29SL400CB100RED |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic 12-Stage Binary Counter 16-CDIP -55 to 125 |
| 中文描述： | 256K X 16 FLASH 1.8V PROM, 100 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 4/44頁 |
| 文件大小： | 945K |
| 代理商： | AM29SL400CB100RED |
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March 3, 2005
A d v a n c e I n f o r m a t i o n
General Description
The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash
memory organized as 524,288 bytes or 262,144
words. The device is offered in 48-pin TSOP and
48-ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data ap-
pears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
volt V
CC
supply. No V
PP
is required for write or erase
operations. The device can also be programmed in
standard EPROM programmers.
The standard device offers access times of 100, 110,
120, and 150 ns, allowing high speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for
the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard
.
Commands are written to the command register
using standard microprocessor write timings. Regis-
ter contents serve as input to an internal state-ma-
chine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase op-
erations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the pro-
gram command sequence. This initiates the
Embed-
ded Program
algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requir-
ing only two write cycles to program data instead of
four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits
. After a program or erase cycle
has been completed, the device is ready to read
array data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affect-
ing the data contents of other sectors. The device is
fully erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sec-
tor protection
feature disables both program and
erase operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data
from, or program data to, any sector that is not se-
lected for erasure. True background erase can thus
be achieved.
The
hardware RESET# pin
terminates any opera-
tion in progress and resets the internal state ma-
chine to reading array data. The RESET# pin may be
tied to the system reset circuitry. A system reset
would thus also reset the device, enabling the sys-
tem microprocessor to read the boot-up firmware
from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode
.
The system can also place the device into the
standby mode
. Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
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| AM29SL400CB100REF | High Speed CMOS Logic 12-Stage Binary Counter 16-CDIP -55 to 125 |
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| AM29SL400CB110WAD | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| AM29SL400CT110WAF | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| AM29SL400CB110WAF | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
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