參數(shù)資料
型號(hào)： AM486DX
英文描述： Am486DX - Am486DX Block Diagram
中文描述： Am486DX - Am486DX框圖
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 1242K
代理商： AM486DX
30
Am486DE2 Microprocessor
Auto Halt Restart
The Auto Halt Restart slot at register offset (word loca-
tion) 7F02h in SMRAM indicates to the SMI handler that
the SMI interrupted the CPU during a HALT state; bit 0
of slot 7F02h is set to 1 if the previous instruction was
a HALT (see Figure 10). If the SMI did not interrupt the
CPU in a HALT state, then the SMI microcode sets bit
0 of the Auto Halt Restart slot to 0. If the previous in-
struction was a HALT, the SMI handler can choose to
either set or reset bit 0. If this bit is set to 1, the RSM
microcode execution forces the processor to reenter the
HALT state. If this bit is set to 0 when the RSM instruction
is executed, the processor continues execution with the
instruction just after the interrupted HALT instruction. If
the HALT instruction is restarted, the CPU will generate
a memory access to fetch the HALT instruction (if it is
not in the internal cache), and execute a HALT bus cycle.
Table 8 shows the possible restart configurations. If the
interrupted instruction was not a HALT instruction (bit 0
is set to 0 in the Auto Halt Restart slot upon SMM entry),
setting bit 0 to 1 will cause unpredictable behavior when
the RSM instruction is executed.
I/O Trap Restart
The I/O instruction restart slot (register offset 7F00h in
SMRAM) gives the SMI handler the option of causing
the RSM instruction to automatically reexecute the in-
terrupted I/O instruction (see Figure 11).
When the RSM instruction is executed, if the I/O instruc-
tion restart slot contains the value 0FFh, then the CPU
automatically reexecutes the l/O instruction that the SMI
signal trapped. If the I/O instruction restart slot contains
the value 00h when the RSM instruction is executed,
then the CPU does not reexecute the I/O instruction.
The CPU automatically initializes the I/O instruction re-
start slot to 00h during SMM entry. The I/O instruction
restart slot should be written only when the processor
has generated an SMI on an I/O instruction boundary.
Processor operation is unpredictable when the I/O in-
struction restart slot is set when the processor is servic-
ing an SMI that originated on a non-I/O instruction
boundary.
If the system executes back-to-back SMI requests, the
second SMI handler must not set the I/O instruction re-
start slot. The second back-to-back SMI signal will not
have the I/O Trap Word set.
I/O Trap Word
The I/O Trap Word contains the address of the I/O ac-
cess that forced the external chipset to assert SMI,
whether it was a read or write access, and whether the
instruction that caused the access to the I/O address
was a valid I/O instruction. Table 9 shows the layout.
Bits 31–16 contain the I/O address that was being ac-
cessed at the time SMI became active. Bits 15–2 are
reserved.
If the instruction that caused the I/O trap to occur was a
valid I/O instruction (IN, OUT, INS, OUTS, REP INS, or
REP OUTS), the Valid I/O Instruction bit is set. If it was
not a valid I/O instruction, the bit is saved as a 0. For
REP instructions, the external chip set should return a
valid SMI within the first access.
Figure 10. Auto Halt Restart Register Offset
Table 8. Auto Halt Restart Configuration
Value
at Entry
Value
at Exit
Processor Action on Exit
0
0
Return to next instruction in interrupted
program
0
1
Unpredictable
1
0
Returns to instruction after HALT
1
1
Returns to interrupted HALT instruction
Auto Halt Restart
Register Offset 7F02h
Reserved
15
1
0
Figure 11. I/O Instruction Restart Register Offset
Table 9. I/O Trap Word Configuration
31–16
15–2
1
0
I/O Address
Reserved
Valid I/O Instruction R/W
15
0
I/O instruction restart slot
Register offset 7F00h
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