參數(shù)資料
型號(hào): AM486DX
英文描述: Am486DX - Am486DX Block Diagram
中文描述: Am486DX - Am486DX框圖
文件頁數(shù): 33/52頁
文件大?。?/td> 1242K
代理商: AM486DX
Am486DE2 Microprocessor
33
A20M Pin
Systems based on the MS-DOS operating system con-
tain a feature that enables the CPU address bit A20 to
be forced to 0. This limits physical memory to a maxi-
mum of 1 Mbyte, and is provided to ensure compatibility
with those programs that relied on the physical address
wraparound functionality of the original IBM PC. The
A20M pin on Am486DE2 CPUs provides this function.
When A20M is active, all external bus cycles drive A20
Low, and all internal cache accesses are performed with
A20 Low.
The A20M pin is recognized while the CPU is in SMM.
The functionality of the A20M input must be recognized
in two instances:
1. If the SMI handler needs to access system memory
space above 1 Mbyte (for example, when saving
memory to disk for a zero-volt suspend), the A20M
pin must be deasserted before the memory above 1
Mbyte is addressed.
2. If SMRAM has been relocated to address space
above 1 Mbyte and A20M is active upon entering
SMM, the CPU attempts to access SMRAM at the
relocated address, but with A20 Low. This could
cause the system to crash, because there would be
no valid SMM interrupt handler at the accessed
location.
Figure 16. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching
EnabledDuring SMM
Figure 17. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching
DisabledDuring SMM
State
Save
SMI Handler
State
Resume
Normal
Cycle
RSM
SMI
SMIACT
FLUSH
SMI
Instruction x
Instruction x+1
Cache contents
invalidated
Cache contents
invalidated
State
Save
SMI Handler
State
Resume
Normal
Cycle
RSM
SMI
SMIACT
FLUSH
SMI
Instruction x
Instruction x+1
Cache contents
invalidated
KEN
相關(guān)PDF資料
PDF描述
AM486DXPGA Am486DX PGA - Am486DX PGA Package Temperature Comparisons
AM486DXSQFP 70NS, PLCC, IND TEMP(EEPROM)
AM486 Am486 Microprocessor Software User's Manual? 4.40MB (PDF)
AM49DL3208G Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
AM49DL320BG Am49DL320BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM486DX/DX2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual
AM486DX2 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family
AM486DX2-66V16BGC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BGI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BHI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP