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參數(shù)資料
| 型號： | AM79C960KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 47/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KCW |
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P R E L I M I N A R Y
AMD
1-389
Am79C960
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board-level continuity test and diag-
nostics. All digital input, output, and input/output pins
are tested. Analog pins, including the AUI differential
driver (DO
±
) and receivers (DI
±
, CI
±
), and the crystal in-
put (XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD
±
, TXP
±
, and receiver RXD
±
are also tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the PCnet-ISA
controller.
Boundary Scan Circuit
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO ), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are pro-
vided for the TDI, TCK, and TMS pins. The TCK pin must
not be left unconnected. The boundary scan circuit re-
mains active during sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An inde-
pendent power-on reset circuit is provided to ensure the
FSM is in the TEST_LOGIC_RESET state at power-up.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See the table
below for a summary of supported instructions.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE in-
struction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers ac-
cording to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used in the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
There are four possible operational modes in the BSR
cell:
1
Capture
2
Shift
3
Update
4
System Function
Other Data Registers
(1) BYPASS REG (1 BIT)
(2) DEV ID REG (32 bits)
Bits 31–28:
Version
Bits 27–12:
Part number (0003H)
Bits 11–1:
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Bit 0:
Always a logic 1
Table: IEEE 1149.1 Supported Instruction Summary
Instruction
Name
Selected
Data Reg
Instruction
Code
Description
Mode
EXTEST
External Test
BSR
Test
0000
IDCODE
ID Code Inspection
ID REG
Normal
0001
SAMPLE
Sample Boundary
BSR
Normal
0010
TRIBYP
Force Tristate
Bypass
Normal
0011
SETBYP
Control Boundary To 1/0
Bypass
Test
0100
BYPASS
Bypass Scan
Bypass
Normal
1111
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