參數(shù)資料
型號(hào)： AM79C960KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁數(shù)： 70/127頁
文件大小： 814K
代理商： AM79C960KCW
P R E L I M I N A R Y
AMD
1-412
Am79C960
CSR68-69: Transmit Status Temporary Storage
Bit
Name
Description
31-0
XSTMP
Transmit Status Temporary Stor-
age location.
Read/write accessible only when
STOP bit is set.
CSR70-71: Temporary Storage
Bit
Name
Description
31-0
TMP8
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
CSR72: Receive Ring Counter
Bit
Name
Description
15-0
RCVRC
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR74: Transmit Ring Counter
Bit
Name
Description
15-0
XMTRC
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR76: Receive Ring Length
Bit
Name
Description
15-0
RCVRL
Receive Ring Length. Contains a
Two’s complement binary num-
ber of the receive descriptor ring
length. This register is initialized
during the PCnet-ISA controller
initialization routine based on the
value in the RLEN field of the
initialization block. This register
can be manually altered; the ac-
tual receive ring length is defined
by the current value in this
register.
Read/write accessible only when
STOP bit is set.
CSR78: Transmit Ring Length
Bit
Name
Description
15-0
XMTRL
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-ISA controller
initialization routine based on the
value in the TLEN field of the ini-
tialization block. This register can
be manually altered; the actual
transmit ring length is defined by
the current value in this register.
Read/write accessible only when
STOP bit is set.
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
15-14
RES
Reserved locations. Read as
ones. Written as zero.
Receive
FIFO
RCVFW controls the point at
which ISA bus receive DMA is re-
quested in relation to the number
of received bytes in the receive
FIFO. RCVFW specifies the
number of bytes which must be
present (once the frame has
been verified as a non-runt) be-
fore receive DMA is requested.
Note however that in order for re-
ceive DMA to be performed for a
new frame, at least 64 bytes must
have been received. This effec-
tively avoids having to react to
receive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature is en-
abled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write accessible only when
STOP bit is set.
13-12RCVFW[1:0]
Watermark.
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