參數(shù)資料
型號(hào)： AM79C960KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 65/127頁(yè)
文件大?。?/td> 814K
代理商： AM79C960KCW
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P R E L I M I N A R Y
AMD
1-407
Am79C960
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT = “1”, the internal twisted
pair receive thresholds are re-
duced by 4.5 dB below the
standard 10BASE-T value (ap-
proximately
3/5)
unsquelch threshold for the RXD
circuit will be 180–312 mV peak.
When LRT = “0”, the unsquelch
threshold for the RXD circuit will
be the standard 10BASE-T
value, 300–520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one half of the unsquelch
threshold.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO- yield “zero” dif-
ferential to operate transformer
coupled loads (Ethernet 2 and
802.3). When TSEL = 1, the DO+
idles at a higher value with re-
spect to DO- , yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
Port Select bits allow for software
controlled selection of the net-
work medium. Medium selection
can be over ridden by the
MAUSEL pin if the XMAUSEL bit
in the ISA Configuration Register
is set.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
The network port configuration
are as follows:
LRT
and
the
TSEL
8-7
PORTSEL
[1:0]
PORTSEL[1:0]
0 0
0 1
1 0
1 1
Network Port
AUI
10BASE-T
GPSI*
Reserved
*Refer to the section on General Purpose Serial Interface for
detailed information on accessing GPSI.
6
INTL
Internal Loopback. See the de-
scription of LOOP, CSR15.2.
Read/write accessible only when
STOP bit is set.
5
DRTY
Disable Retry. When DRTY = “1”,
PCnet-ISA controller will attempt
only one transmission. If DRTY =
“0”, PCnet-ISA controller will
attempt 16 retry attempts before
signaling a retry error.
Read/write accessible only when
STOP bit is set.
4
FCOLL
Force Collision. This bit allows
the collision logic to be tested.
PCnet-ISA controller must be in
internal loopback for FCOLL to
be valid. If FCOLL = “1”, a colli-
sion will be forced during
loopback transmission attempts;
a Retry Error will ultimately re-
sult. If FCOLL = “0”, the Force
Collision logic will be disabled.
Read/write accessible only when
STOP bit is set.
3
DXMTFCS
Disable Transmit CRC (FCS).
When DXMTFCS = 0, the trans-
mitter will generate and append a
FCS to the transmitted frame.
When DXMTFCS = 1, the FCS
logic is allocated to the receiver
and no FCS is generated or sent
with the transmitted frame.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set, no
FCS will be generated. If both
DXMTFCS is set and ADD_FCS
is clear for a particular frame, no
FCS
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
will
be
generated. If
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