參數(shù)資料
型號(hào): AM79C971VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述: 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁(yè)數(shù): 142/265頁(yè)
文件大?。?/td> 3190K
代理商: AM79C971VCW
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142
Am79C971
P R E L I M I N A R Y
CSR72: Receive Ring Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCVRC
Receive Ring Counter location.
Contains a two
s complement bi-
nary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR74: Transmit Ring Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRC
Transmit Ring Counter location.
Contains a two
s complement bi-
nary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR76: Receive Ring Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCVRL
Receive Ring Length. Contains
the two
s complement of the re-
ceive descriptor ring length. This
register is initialized during the
Am79C971 controller initializa-
tion routine based on the value in
the RLEN field of the initialization
block. However, this register can
be manually altered. The actual
receive ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR78: Transmit Ring Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRL
Transmit Ring Length. Contains
the two
s complement of the
transmit descriptor ring length.
This register is initialized during
the Am79C971 controller initial-
ization routine based on the value
in the TLEN field of the initializa-
tion block. However, this register
can be manually altered. The ac-
tual transmit ring length is defined
by the current value in this regis-
ter. The ring length can be de-
fined as any value from 1 to
65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-14 RES
Reserved locations. Written as
zeros and read as undefined.
13-12 RCVFW[1:0] Receive
FIFO
Watermark.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
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