參數(shù)資料
型號: AM79C971VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述: 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁數(shù): 179/265頁
文件大?。?/td> 3190K
代理商: AM79C971VCW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁當(dāng)前第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁
Am79C971
179
P R E L I M I N A R Y
bit will allow the Am79C971 con-
troller to work seamlessly with the
Micro Linear 6692 PHY. See the
section on
Working with Micro
Linear 6692
for details.
Read/Write accessible always.
MII
μ
L is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit. MII
μ
L is only
valid when the internal Network
Port Manager is scanning for a
network port.
1
MIIILP
Media Independent Interface In-
ternal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loopback
on itself. The interface is mapped
in
the
following
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR
d with TX_EN and
RX_DV and always encompass-
es the transmit frame. TX_ER is
looped back as RX_ER. Howev-
er, TX_ER will not get asserted
by the Am79C971 controller to
signal an error. The TX_ER func-
tion is reserved for future use.
way.
The
Read/Write accessible always.
MIIILP is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
0
FCON
Fast Configuration Mode. When
set this bit will force the internal
Management Port State Machine
into a Fast Configuration Mode.
During this mode, the Manage-
ment Port State Machine will not
attempt to start Auto-Negotiation
on the internal as well as the ex-
ternal PHY. Instead, it will rely on
link beats for link pass state. This
will accelerate the automatic port
selection on the Am79C971 con-
troller.
Read/Write accessible always.
FCON is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit. FCON is only
valid when the internal Network
Port Manager is scanning for a
network port. See Table 40.
BCR33: MII Address Register
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
9-5
PHYAD
MII Management Frame PHY Ad-
dress. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII manage-
ment port pins (MDC and MDIO)
whenever a read or write transac-
tion occurs to BCR34. The inter-
nal PHY device is always
addressed as 11111b. The MII
management frame will not ap-
pear on the MII when reading or
writing to the internal PHY. This is
done for MII compatibility sake.
The Network Port Manager cop-
ies
the
PHYAD
Am79C971 controller reads the
EEPROM and uses it to commu-
nicate with the external PHY. The
PHY address must be pro-
grammed into the EEPROM prior
to starting the Am79C971 con-
troller.
after
the
Read/Write accessible always.
PHYAD
is
undefined
H_RESET and is unaffected by
S_RESET and the STOP bit.
after
4-0
REGAD
MII Management Frame Register
Address. REGAD contains the 5-
bit Register Address field that is
used in the management frame
that gets clocked out via the MII
management port pins (MDC and
MDIO) whenever a read or write
transaction occurs to BCR34.
Read/Write accessible always.
REGAD
is
undefined
H_RESET and is unaffected by
S_RESET and the STOP bit.
after
相關(guān)PDF資料
PDF描述
AM79C971 PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C972 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKC\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKD/W 制造商:Advanced Micro Devices 功能描述: