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參數(shù)資料
| 型號(hào)： | AM79C972BVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 18/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVIW |
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18
Am79C972
REQ
Bus Request
The Am79C972 controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the Am79C972 controller does not request
the bus. In Power Management mode, the REQ pin will
not be driven.
Input/Output
When RST is active, REQ is an input for NAND tree
testing
.
RST
Reset
When RST is asserted LOW and the PG pin is HIGH,
then the Am79C972 controller performs an internal
system
reset
of
the
(HARDWARE_RESET, see section on RESET). RST
must be held for a minimum of 30 clock periods. While
in the H_RESET state, the Am79C972 controller will
disable or deassert all outputs. RST may be asynchro-
nous to clock when asserted or deasserted.
Input
type
H_RESET
When the PG pin is LOW, RST disables all of the PCI
pins except the PME pin.
When RST is LOW and PG is HIGH, NAND tree testing
is enabled.
SERR
System Error
During any slave transaction, the Am79C972 controller
asserts SERR when it detects an address parity error,
and reporting of the error is enabled by setting PER-
REN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.
Output
By default SERR is an open-drain output. For compo-
nent test, it can be programmed to be an active-high
totem-pole output.
When RST is active, SERR is an input for NAND tree
testing
.
STOP
Stop
In slave mode, the Am79C972 controller drives the
STOP signal to inform the bus master to stop the cur-
rent transaction. In bus master mode, the Am79C972
controller checks STOP to determine if the target wants
to disconnect the current transaction.
Input/Output
When RST is active, STOP is an input for NAND tree
testing
.
TRDY
Target Ready
TRDY indicates the ability of the target of the transac-
tion to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simul-
Input/Output
taneously. A data phase is completed on any clock
when both IRDY and TRDY are asserted.
When the Am79C972 controller is a bus master, it
checks TRDY during all read data phases to determine
if valid data is present on AD[31:0]. During all write data
phases, the device checks TRDY to determine if the
target is ready to accept the data.
When the Am79C972 controller is the target of a trans-
action, it asserts TRDY during all read data phases to
indicate that valid data is present on AD[31:0]. During
all write data phases, the device asserts TRDY to indi-
cate that it is ready to accept the data.
When RST is active, TRDY is an input for NAND tree
testing
.
PME
Power Management Event Output, Open Drain
PME is an output that can be used to indicate that a
power management event (a Magic Packet, an OnNow
pattern match, or a change in link state) has been de-
tected. The PME pin is asserted when either
1. PME_STATUS and PME_EN are both 1,
2. PME_EN_OVR and MPMAT are both 1, or
3. PME_EN_OVR and LCDET are both 1.
The PME signal is asynchronous with respect to the
PCI clock.
Board Interface
Note:
Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12.
LED0
LED0
This output is designed to directly drive an LED. By de-
fault, LED0 indicates an active link connection. This pin
can also be programmed to indicate other network sta-
tus (see BCR4). The LED0 pin polarity is programma-
ble, but by default it is active LOW. When the LED0 pin
polarity is programmed to active LOW, the output is an
open drain driver. When the LED0 pin polarity is pro-
grammed to active HIGH, the output is a totem pole
driver.
Output
Note:
The LED0 pin is multiplexed with the EEDI pin.
LED1
LED1
This output is designed to directly drive an LED. By de-
fault, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other net-
work status (see BCR5). The LED1 pin polarity is pro-
grammable, but by default, it is active LOW. When the
LED1 pin polarity is programmed to active LOW, the
output is an open drain driver. When the LED1 pin po-
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C974 | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KCW | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
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