參數(shù)資料
型號(hào)： AM79C976
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
中文描述： PCnet -專業(yè)⑩個(gè)10/100Mbps PCI以太網(wǎng)控制器
文件頁(yè)數(shù)： 27/309頁(yè)
文件大小： 2070K
代理商： AM79C976
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8/01/00
Am79C976
27
P R E L I M I N A R Y
This pin can drive the external system management
logic that causes the CPU to get out of a low power
mode of operation. This pin is implemented for designs
that do not support the PME function.
Three bits that are loaded from the EEPROM into
CSR116 can program the characteristics of this pin:
1. RWU_POL determines the polarity of the RWU sig-
nal.
2. If RWU_GATE bit is set, RWU is forced to the high
impedance state when PG input is LOW.
3. RWU_DRIVER determines whether the output is
open drain or totem pole.
The internal power-on-reset signal forces this output
into the high impedance state until after the polarity and
drive type have been determined.
WUMI
Wake-Up Mode Indicator
Open Drain
This output, which is capable of driving an LED, is as-
serted when the device is in Magic Packet mode. It can
be used to drive external logic that switches the device
power source from the main power supply to an auxil-
iary power supply.
VAUX_SENSE
3.3 Vaux Presence Sense
The signal on this pin is logically anded with bit 15 of
the PCI PMC register when the PMC register is read.
This pin should normally be connected to the PCI
3.3 Vaux pin. This allows the PMC register to indicate
that the device is capable of supporting PME from the
D3
cold
state only when the 3.3 Vaux pin is supplying
power.
CLKSEL0
Clock Select 0
The Am79C976 system clock can either be driven by
an external clock generator connected to the XCLK pin
or by an internal clock generator timed by a 25-MHz
crystal connected between the XTAL1 and XTAL2 pins.
The CLKSEL0 and CLKSEL1 pins select the source of
the system clock and the frequency at which the exter-
nal clock generator must run. In addition, CLKSEL0
and CLKSEL1 determine the frequency of ERCLK, the
external SSRAM clock. Table 1 shows the possible
combinations.
CLKSEL1
Clock Select 1
The Am79C976 system clock can either be driven by
an external clock generator connected to the XCLK pin
or by an internal clock generator timed by a 25-MHz
crystal connected between the XTAL1 and XTAL2 pins.
The CLKSEL0 and CLKSEL1 pins select the source of
Output,
Input
Input
Input
the system clock and the frequency at which the exter-
nal clock generator must run. In addition CLKSEL0 and
CLKSEL1 determine the frequency of ERCLK, the ex-
ternal SSRAM clock. Table 1 shows the possible com-
binations.
CLKSEL2
Clock Select 2
The CLKSEL2 pin must be held low during normal op-
eration.
TEST
Test Reset
The TEST pin must be held low during normal opera-
tion.
XCLK
External Clock Input
The Am79C976 system clock can either be driven by
an external clock generator connected to this pin or by
a 25-MHz crystal connected between the XTAL1 and
XTAL2 pins, depending on the state of the CLKSEL0
and CLKSEL1 pins. When either CLKSEL0 or
CLKSEL1 or both are held high, a 20-, 25-, or
33
1
/
3
-MHz
clock signal must be applied to XCLK as
shown in Table 1. When CLKSEL0 and CLKSEL1 are
both held low, the XCLK pin should be connected to ei-
ther VSS or VDD.
Input
Input
Input
Table 1. System Clock Selections
XTAL1
Crystal
If the CLKSEL0 and CLKSEL1 pins are both held low,
a 25-MHz crystal should be connected between the
XTAL1 pin and the XTAL2 pin. This crystal controls the
frequency of the internal clock-generator circuit.
Input
If the CLKSEL0 and CLKSEL1 pins are not both held
low, a 20-, 25-, or
33
1
/
3
-MHz
clock source must be con-
CLKSEL2 CLKSEL1 CLKSEL0
CLOCK
SOURCE
ERCLK
(MHz)
1
X
X
Design Factory
Test Only.
0
0
0
25-MHz
Crystal,
XTAL1,XT
AL2
87.5
0
0
1
XCLK, 20
MHz
90
0
1
0
XCLK, 25
MHz
87.5
0
1
1
XCLK,
33
1
/
3
MHz
82.5
相關(guān)PDF資料
PDF描述
AM79C976KIW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C976KC 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk
AM79C976KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KD 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC)
AM79C976KF 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
AM79C976KI 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
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