
46
Functional Operation
Chapter 5
AMD-751
System Controller Data Sheet
21910D
—
August 1999
Preliminary Information
Address Map
Table 7 shows the AMD-751 system controller address map.
Table 7.
AMD-751
System Controller Memory Address Map
Address Space Start Address Space End Name/Command
PA msb =0 and
1 FF00 0000
3 FFFF FFFF
Description
PA msb =0 and
Reserved
(Masked)
Reserved for use by the AMD-751 system controller.
PA msb =0 and
1 FE00 0000
PA msb =0 and
1 FEFF FFFF
PCI Configuration
Space (Masked)
This space is used to create PCI configuration cycles
using WrBytes, WrLWs, RdBytes, and RdLWs commands
only. See
“
PCI Configuration
”
on page 79.
This space is used to create PCI I/O cycles using
WrBytesWrLWs, RdBytes, and RdLWs commands only.
WrLWs commands to this space are used to create PCI
special cycles. The lower 32 bits of the data are passed
on to the PCI bus as both the address and data with the
special-cycle PCI command. See Table 8 on page 48 for
all special cycles generated by the processor. RdBytes
commands to this space are used to create PCI IACK.
The lower 16 bits of these addresses are passed on to
the PCI unmodified with the IACK PCI command. See
“
PCI Configuration Accesses
”
on page 50.
PA msb =0 and
1 FC00 0000
PA msb =0 and
1 FDFF FFFF
PCI I/O Space
(Masked)
PA msb =0 and
1 F800 0000
PA msb =0 and
1 FBFF FFFF
PCI IACK/Special
Cycle Generation
(Masked)
PA msb =0 and
1 0000 0000
PA msb =0 and
1 F7FF FFFF
Reserved
(Masked)
Reserved for use by the AMD-751.
PA msb =0 and
0 0000 0000
PA msb =0 and
0 FFFF FFFF
PCI Memory
Space
(Masked)
The lower 32-bits of these addresses are forwarded,
unmodified, to the PCI and are accessed with
Wr/RdBytes, Wr/RdLWs, or Wr/RdQWs only. The
AMD-751 generates low-order address bits required by
the AMD Athlon system bus MASK field.
DRAM, accessed with masked write commands
WrBytes, WrLWs, and WrQWs only.
The AMD-751 does not support masked reads to this
address space.
This address space can be used by the AMD-751 for
undefined purposes.
DRAM, accessed with read and write block commands.
PA msb =1 and
0 0000 0000
PA msb =1 and
0 0000 0000
PA msb =1 and
0 FF000 0000
PA msb =1 and
3 FFFF FFFF
PA msb =1 and
3 FFFF FFFF
PA msb =1 and
3 FFFF FFFF
Normal Memory
(Masked Writes)
Reserved
(Masked Reads)
Reserved
(Blocks)
PA msb = 0 and
0 0000 0000
PA msb = 0 and
3 FFFF FFFF
Normal Memory
(Blocks)
Note:
The AMD-751 only uses 32 address bits internally and
the address space wraps. Address 1 0000 0000 is
treated the same as 0 0000 0000.
Note:
msb = Most Significant Bit