Chapter 9
Cache Organization
227
23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
9.12
Writethrough and Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-2E+ processor
L1 data cache and the L2 cache. The following conditions apply
to both the writethrough and writeback modes:
s
Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
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Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
Shared and invalid MESI lines are in the writethrough
state.
Modified and exclusive MESI lines are in the writeback
state.
9.13
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in Real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
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Cache-line fills (caused by read misses or write allocates)
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Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
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Internal snoops
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Inquire cycles
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The FLUSH# signal