ProASICPLUS Flash Family FPGAs 2- 74 v5.9 V
參數(shù)資料
型號： APA075-PQG208I
廠商： Microsemi SoC
文件頁數(shù)： 162/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 75K 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 27648
輸入/輸出數(shù)： 158
門數(shù)： 75000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
2- 74
v5.9
VPP
Programming Supply Pin
This pin may be connected to any voltage between GND
and 16.5 V during normal operation, or it can be left
unconnected.2 For information on using this pin during
programming,
see
the
ProASICPLUS Devices application note. Actel recommends
floating the pin or connecting it to VDDP.
VPN
Programming Supply Pin
This pin may be connected to any voltage between 0.5 V
and –13.8 V during normal operation, or it can be left
unconnected.3 For information on using this pin during
programming,
see
the
ProASICPLUS Devices application note. Actel recommends
floating the pin or connecting it to GND.
Recommended Design Practice
for VPN/VPP
ProASICPLUS Devices – APA450, APA600,
APA750, APA1000
Bypass capacitors are required from VPP to GND and VPN
to GND for all ProASICPLUS devices during programming.
During the erase cycle, ProASICPLUS devices may have
current surges on the VPP and VPN power supplies. The
only way to maintain the integrity of the power
distribution to the ProASICPLUS device during these
current surges is to counteract the inductance of the
finite length conductors that distribute the power to the
device. This can be accomplished by providing sufficient
bypass capacitance between the VPP and VPN pins and
GND (using the shortest paths possible). Without
sufficient
bypass
capacitance
to
counteract
the
inductance, the VPP and VPN pins may incur a voltage
spike beyond the voltage that the device can withstand.
This issue applies to all programming configurations.
The solution prevents spikes from damaging the
ProASICPLUS devices. Bypass capacitors are required for
the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic
capacitor with a 25 V or greater rating. To filter low-
frequency noise (decoupling), use a 4.7 F (low ESR, <1
<
Ω, tantalum, 25 V or greater rating) capacitor. The
capacitors should be located as close to the device pins as
possible (within 2.5 cm is desirable). The smaller, high-
frequency capacitor should be placed closer to the device
pins than the larger low-frequency capacitor. The same
dual-capacitor circuit should be used on both the VPP and
VPN pins (Figure 2-46).
ProASICPLUS Devices – APA075, APA150,
APA300
These devices do not require bypass capacitors on the VPP
and VPN pins as long as the total combined distance of
the programming cable and the trace length on the
board is less than or equal to 30 inches. Note: For trace
lengths greater than 30 inches, use the bypass capacitor
recommendations in the previous section.
2. There is a nominal 40 k
Ω pull-up resistor on V
PP.
3. There is a nominal 40 k
Ω pull-down resistor on V
PN.
Figure 2-46 ProASICPLUS VPP and VPN Capacitor Requirements
2.5cm
0.1 F
to
0.01 F
Programming
Header
or
Supplies
4.7 F
Actel
ProASIC
Device
+
_
V
PP
V
PN
+
_
0.1 F
to
0.01 F
4.7 F
PLUS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA075-PQGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-PQGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-PQGI 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-PQGM 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-PQGPP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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