- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4476 > APA075-PQG208I (Microsemi SoC)IC FPGA PROASIC+ 75K 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | APA075-PQG208I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 92/178頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA PROASIC+ 75K 208-PQFP |
| 標準包裝： | 24 |
| 系列： | ProASICPLUS |
| RAM 位總計： | 27648 |
| 輸入/輸出數(shù)： | 158 |
| 門數(shù)： | 75000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁當前第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁
ProASICPLUS Flash Family FPGAs
2- 10
v5.9
Timing Control and
Characteristics
ProASICPLUS Clock Management System
ProASICPLUS devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASICPLUS family contains two phase-locked loop (PLL)
blocks which perform the following functions:
Clock Phase Adjustment via Programmable Delay
(250 ps steps from –7 ns to +8 ns)
Clock Skew Minimization
Clock Frequency Synthesis
Each PLL has the following key features:
Input Frequency Range (fIN) = 1.5 to 180 MHz
Feedback Frequency Range (fVCO) = 24 to 180 MHz
Output Frequency Range (fOUT) = 8 to 180 MHz
Output Phase Shift = 0 ° and 180 °
Output Duty Cycle = 50%
Low Output Jitter (maximum at 25°C)
–fVCO <10 MHz. Jitter ±1% or better
–
10 MHz < fVCO < 60 MHz. Jitter ±2% or better
–fVCO > 60 MHz. Jitter ±1% or better
Note: Jitter (ps) = Jitter (%) × period
For Example:
Low Power Consumption – 6.9 mW (max. – analog
supply) + 7.0 W/MHz (max. – digital supply)
Physical Implementation
Each side of the chip contains a clock conditioning circuit
based on a 180 MHz PLL block (Figure 2-11 on page
2-11). Two global multiplexed lines extend along each
side of the chip to provide bidirectional access to the PLL
on that side (neither MUX can be connected to the
opposite side's PLL). Each global line has optional LVPECL
input pads (described below). The global lines may be
driven by either the LVPECL global input pad or the
outputs from the PLL block, or both. Each global line can
be driven by a different output from the PLL. Unused
global pins can be configured as regular I/Os or left
unconnected. They default to an input with pull-up. The
two signals available to drive the global networks are as
12, and Table 2-8 on page 2-13):
Global A (secondary clock)
Output from Global MUX A
Conditioned version of PLL output (fOUT) – delayed
or advanced
Divided version of either of the above
Further delayed version of either of the above
(0.25 ns, 0.50 ns, or 4.00 ns delay)1
Global B
Output from Global MUX B
Delayed or advanced version of fOUT
Divided version of either of the above
Further delayed version of either of the above
(0.25 ns, 0.50 ns, or 4.00 ns delay)2
Functional Description
Each PLL block contains four programmable dividers as
shown in Figure 2-11 on page 2-11. These allow
frequency scaling of the input clock signal as follows:
The n divider divides the input clock by integer
factors from 1 to 32.
The m divider in the feedback path allows
multiplication of the input clock by integer factors
ranging from 1 to 64.
The two dividers together can implement any
combination
of
multiplication
and
division
resulting in a clock frequency between 24 and 180
MHz exiting the PLL core. This clock has a fixed
50% duty cycle.
The output frequency of the PLL core is given by
frequency):
fOUT = fREF × m ÷ n
EQ 2-1
The third and fourth dividers (u and v) permit the
signals applied to the global network to each be
further divided by integer factors ranging from 1
to 4.
the user to define a wide range of frequency multiplier
and divisors.
EQ 2-2
EQ 2-3
Jitter in picoseconds at 100 MHz = 0.01 × (1/100E6) = 100 ps
Maximum Acquisition
Time
= 80 s for fVCO > 40 MHz
= 30 s for fVCO < 40 MHz
1. This mode is available through the delay feature of the global MUX driver.
f
GLB
m
nu
×
()
-----------------
=
f
GLA
m
nv
×
()
-----------------
=
相關PDF資料 |
PDF描述 |
|---|---|
| RSA50DRSI-S288 | CONN EDGECARD 100PS .125 EXTEND |
| APA075-PQ208I | IC FPGA PROASIC+ 75K 208-PQFP |
| A40MX04-3VQ80 | IC FPGA MX SGL CHIP 6K 80-VQFP |
| IDT71V3578S133PFG | IC SRAM 4MBIT 133MHZ 100TQFP |
| A40MX04-3VQG80 | IC FPGA MX SGL CHIP 6K 80-VQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| APA075-PQGB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-PQGES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-PQGI | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-PQGM | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-PQGPP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復。