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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡指令集微處理器） |
| 文件頁數(shù)： | 43/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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Instruction Set - LDR, STR
39
4.7.6 Data Aborts
A transfer to or from a legal address may cause problems for a memory management system. For instance,
in a system which uses virtual memory the required data may be absent from main memory. The memory
manager can signal a problem by taking the processor
ABORT input HIGH whereupon the Data Abort trap
will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be
restarted and the original program continued.
ARM60 supports two types of Data Abort processing depending on the
LATEABT
control signal. When set
for Early
Aborts, any base register write-back which would have occurred is prevented in the event of an
abort. When configured for Late
Aborts, this write-back is allowed to take place and the
Abort handler must
correct this before allowing the instruction to be re-executed.
4.7.7 Instruction Cycle Times
Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N
and I are as defined in section 5.1 Cycle types on page 65.
STR instructions take 2N incremental cycles to execute.
4.7.8 Assembler syntax
<LDR|STR>{cond}{B}{T} Rd,<Address>
LDR - load from memory into a register
STR - store from a register into memory
{cond} - two-character condition mnemonic, see
Figure 6: Condition Codes
{B} - if B is present then byte transfer, otherwise word transfer
{T} - if T is present the W bit will be set in a post-indexed instruction, forcing non-privileged mode for the
transfer cycle. T is not allowed when a pre-indexed addressing mode is specified or implied.
Rd is an expression evaluating to a valid register number.
<Address> can be:
(i)
An expression which generates an address:
<expression>
The assembler will attempt to generate an instruction using the PC as a base and a corrected
immediate offset to address the location given by evaluating the expression. This will be a PC
relative, pre-indexed address. If the address is out of range, an error will be generated.
(ii)
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
offset of <expression> bytes
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