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| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁(yè)數(shù)： | 96/121頁(yè) |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
92
When the HIGHZ instruction is loaded into the instruction register, all outputs are placed in an inactive
drive state.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is
shifted into the bypass register via
TDI
and out via
TDO
bit shifted out will be a zero. The bypass register is not affected in the UPDATE-DR state.
after a delay of one
TCK
cycle. Note that the first
8.5.5 CLAMPZ (1001)
The CLAMPZ instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the CLAMPZ instruction is loaded into the instruction register, all outputs are placed in an inactive
drive state, but the data supplied to the disabled output drivers is derived from the boundary-scan cells.
The purpose of this instruction is to ensure, during production testing, that each output driver can be
disabled when its data input is either a 0 or a 1.
A guarding pattern (specified for this device at the end of this section) should be pre-loaded into the
boundary-scan register using the SAMPLE/PRELOAD instruction prior to selecting the CLAMPZ
instruction.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is
shifted into the bypass register via
TDI
and out via
TDO
bit shifted out will be a zero. The bypass register is not affected in the UPDATE-DR state.
after a delay of one
TCK
cycle. Note that the first
8.5.6 INTEST (1100)
The BS (boundary-scan) register is placed in test mode by the INTEST instruction.
The INTEST instruction connects the BS register between
TDI
and
TDO
.
When the instruction register is loaded with the INTEST instruction, all the boundary-scan cells are placed
in their test mode of operation.
In the CAPTURE-DR state, the complement of the data supplied to the core logic from input boundary-scan
cells is captured, while the true value of the data that is output from the core logic to output boundary- scan
cells is captured. Note that CAPTURE-DR captures the complemented value of the input cells for testability
reasons.
In the SHIFT-DR state, the previously captured test data is shifted out of the BS register via the
whilst new test data is shifted in via the
TDI
pin to the BS register parallel input latch. In the UPDATE-DR
state, the new test data is transferred into the BS register parallel output latch. Note that this data is applied
immediately to the system logic and system pins. The first INTEST vector should be clocked into the
boundary-scan register, using the SAMPLE/PRELOAD instruction, prior to selecting INTEST to ensure
that known data is applied to the system logic.
TDO
pin,
Single-step operation is possible using the INTEST instruction.
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