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| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁(yè)數(shù)： | 94/121頁(yè) |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
90
8.2 Reset
The boundary-scan interface includes a state-machine controller (the TAP controller). In order to force the
TAP controller into the correct state after power-up of the device, a reset pulse must be applied to the
nTRST
pin. If the boundary scan interface is to be used, then
again. If the boundary scan interface is not to be used, then the
Note that a clock on
TCK
is not necessary to reset the device.
nTRST
nTRST
must be driven LOW, and then HIGH
pin may be tied permanently LOW.
The action of reset (either a pulse or a DC level) is as follows:
System mode is selected (i.e. the boundary scan chain does NOT intercept any of the signals passing
between the pads and the core).
IDcode mode is selected. If
Fig 32), the IDcode will be clocked out of
TMS
and
TCK
are used to put the TAP controller in
TDO
.
Shift-DR
mode (see
8.3 Pullup Resistors
TDI, TMS, nTRST and TCK all have on-chip pullup resistors.
8.4 Instruction Register
The instruction register is 4 bits in length.
There is no parity bit. The fixed value loaded into the instruction register during the CAPTURE-IR
controller state is: 0001.
8.5 Public Instructions
The following public instructions are supported:
Instruction
Binary Code
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
CLAMPZ
INTEST
IDCODE
BYPASS
0000
0011
0101
0111
1001
1100
1110
1111
In the descriptions that follow,
transitions on
TDO
TDI
and
TMS
are sampled on the rising edge of
TCK
.
TCK
and all output
occur as a result of the falling edge of
8.5.1 EXTEST (0000)
The BS (boundary-scan) register is placed in test mode by the EXTEST instruction.
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