Table 34 provides valid combinations of Modulato" />
參數(shù)資料
型號(hào)： AS8510-ASST-500
廠商： ams
文件頁(yè)數(shù)： 35/47頁(yè)
文件大小： 0K
描述： IC BATTERY MANAGEMENT 20-SSOP
產(chǎn)品培訓(xùn)模塊： AS8510 Data Acquisition IC
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 電池管理
輸入類(lèi)型： 模擬，數(shù)字
輸出類(lèi)型： 模擬，數(shù)字
接口： SPI 串行
電流 - 電源： 5.5mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： AS8510-ASST-500DKR
Revision 3.5
39 - 46
AS8510
Datasheet - Detailed Descr i p ti on
Table 34 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and
TADC.
7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into
initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500
μsec, and, during this period, INT pin toggles at the
rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
activation should be carried out only after the initialization period. See Figure 17 for the timing details of the sequence of device initialization on
soft-reset.
Figure 17. AS8510 Device Initialization Sequence at Soft-reset
7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers
will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the
clock needs to be disabled.
Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
Modulator Clock
Chopper Frequency
CHOP_CLK
Decimation Ratio R1
TDATA_STATUS_RD
TADC
R2/(2*CHOP_CLK)
for R2=4
1.024MHz
2KHz
64
1usec * 64 * [4 - 2.5] = 96usec
1mSec
2.048MHz
2KHz
64
0.5usec * 64 * [8 - 2.5] = 176usec
1mSec
2.048MHz
2KHz
128
0.5usec * 128 * [4 - 2.5] = 96usec
1mSec
2.048MHz
4KHz
64
0.5usec * 64 * [4 - 2.5] = 48usec
0.5mSec
DATA-N
DATA-N+1
D4
D1
D2
D3
D4
D1
TDATA_STATUS_RD
TDATA_VALID
TDATA_INVALID
Re-Configure
Device
Start
ADC
INT
CHOP_CLK
Channel Data
Register
0x0000
DATA1
DATA2
D1
D2
D
3
D4
D1
D2
D3
D4
D1
D2
D3
D4
500S
1.5mS
TDATA_STATUS_RD
TDATA_VALID
TDATA_INVALID
Soft Reset
UsingD7
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