參數(shù)資料
型號(hào)： AT17LV040-10BJC
廠商： ATMEL CORP
元件分類： PROM
英文描述： FPGA Configuration EEPROM Memory
中文描述： 4M X 1 CONFIGURATION MEMORY, PQCC44
封裝： PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù)： 28/29頁(yè)
文件大?。?/td> 412K
代理商： AT17LV040-10BJC
8
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
4.1
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
4.3
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
4.4
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
4.5
WP
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP
is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on AT17LV65/128/256 devices.
4.6
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010 devices.
4.7
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low).
4.8
GND
Ground pin. A 0.2 F decoupling capacitor between V
CC and GND is recommended.
4.9
CEO
Chip Enable Output (active Low). This output goes Low when the address counter has reached
its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It will stay Low as long as CE is
Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until
the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device.
相關(guān)PDF資料
PDF描述
AT17LV128-10BJC FPGA Configuration EEPROM Memory
AT17LV256-10BJC PhotoMOS Relay; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:5V RoHS Compliant: No
AT17LV512-10BJC FPGA Configuration EEPROM Memory
AT17LV65A-10BJC FPGA Configuration EEPROM Memory
AT24C08SC-09BT 1K X 8 I2C/2-WIRE SERIAL EEPROM, XMA8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT17LV040-10BJI 功能描述:FPGA-配置存儲(chǔ)器 Serial EEPROM RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20
AT17LV040-10CC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV040-10CI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV040-10JC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV040-10JI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
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